A chip structure is provided. The chip structure includes a substrate. The clip structure includes a conductive line over the substrate. The chip structure includes a first passivation layer over the substrate and the conductive line. The chip structure includes a conductive pad over the first passivation layer covering the conductive line. The conductive pad is thicker and wider than the conductive line. The chip structure includes a first conductive via structure and a second conductive via structure passing through the first passivation layer and directly connected between the conductive pad and the conductive line. The chip structure includes a conductive pillar over the conductive pad.

The present invention relates to structure and formation of side walls in micro devices. The structure allows access of one side of the micro device to another side through conductive layers and pads. In particular, the top and bottom sides of the micro devices are in direction of the current in the device and sidewalls are isolation surfaces surrounding the top and bottom sides of the device.

Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the substrate, a TSV structure passing through the first interlayer insulating layer and the substrate. The TSV structure has a bottom end protruding from a back-side of the substrate, a back-side insulating layer and a back-side passivation layer disposed on the back-side of the substrate, and a bumping pad buried in the back-side insulating layer and the back-side passivation layer and disposed on the bottom end of the TSV structure. The bottom end of the TSV structure protrudes into the back-side bumping pad, and top surfaces of the back-side passivation layer and the back-side bumping pad are coplanar.

A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.

In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10.sup.−6 m.) and approximately 10 micron (10.sup.−5 m.) from each one of said converging sides landing on an underlying metal layer.

A semiconductor device includes a semiconductor substrate including a circuit layer disposed therein, a bonding pad disposed on the semiconductor substrate, the bonding pad being electrically connected to the circuit layer, and a metal layer electrically connected to the bonding pad. The metal layer includes a first via electrically connected to the bonding pad, the first via providing an electrical path between the metal layer and the circuit layer, and a second via protruding toward the semiconductor substrate, the second via supporting the metal layer on the semiconductor substrate.

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

A resistive element includes: a semiconductor substrate; a lower insulating film deposited on the semiconductor substrate; a resistive layer deposited on the lower insulating film; an interlayer insulating film covering the resistive layer; a pad-forming electrode deposited on the interlayer insulating film, and including a first edge portion connected to one edge portion of the resistive layer and a second edge portion opposite to the first edge portion to be in electrical Schottky contact with the semiconductor substrate; a relay wire having one edge connected to another edge portion of the resistive layer to form an ohmic contact to the semiconductor substrate; and a counter electrode provided under the semiconductor substrate, wherein the resistive element uses a resistance value between the pad-forming electrode and the counter electrode.

A semiconductor device according to the present disclosure includes a semiconductor substrate, a first electrode provided on the semiconductor substrate, an insulating layer including a first part provided on an upper surface of the first electrode, a second electrode including a main portion and an eaves portion, the main portion being provided on the upper surface of the first electrode, the eaves portion extending over the first part and solder covering an upper surface of the main portion and a part of an upper surface of the eaves portion wherein the insulating layer includes a second part covering a part of the upper surface of the eaves portion, the part being closer to an end portion of the eaves portion than the part covered by the solder and a third part connecting the first part and the second part and covering the end portion of the eaves portion.

A semiconductor device package includes a first electronic component having a first surface and a second surface opposite the first surface. The semiconductor device package further includes a first pad disposed on the first surface of the first electronic component. The first pad has a first surface facing away from the first surface of the first electronic component, a second surface opposite the first surface of the first pad, and a lateral surface extended between the first surface of the first pad and the second surface of the first pad. The semiconductor device package further includes a second pad disposed on the first surface of the first pad. The second pad has a first surface facing away from the first surface of the first pad, a second surface opposite the first surface of the second pad, and a lateral surface extended between the first surface of the second pad and the second surface of the second pad. A width of the first surface of the second pad is greater than a width of the second surface of the second pad. A method of manufacturing a semiconductor device package is also disclosed.