A semiconductor package includes: a first semiconductor chip; a second semiconductor chip; and a bonding structure at an interface between the first and second semiconductor chips. The bonding structure includes: a first bonding insulating layer on the first semiconductor chip; a first connection pad in a first pad opening formed in the first bonding insulating layer, the first connection pad including a first pad layer, a first interface layer including a copper oxide, and a first capping layer; a second bonding insulating layer on the second semiconductor chip; and a second connection pad in a second pad opening formed in the second bonding insulating layer, the second connection pad including a second pad layer, a second interface layer including a copper oxide, and a second capping layer. The first and second capping layers include copper monocrystal layers having a (111) orientation.

The present disclosure relates to a display panel, a display device and a manufacturing method of a display panel. The display panel includes: a display substrate having a display area and a non-display area, the display substrate including a substrate and an IC bonding portion which includes: a pin; a first passivation layer located on one side of the substrate adjacent to the pin and covering a peripheral area of the pin, and exposing a central area of the pin; a first barrier layer located on one side of the first passivation layer away from the substrate and covered at the first passivation layer and an edge of the first passivation layer connected to the pin; and a first metal layer located on one side of the first barrier layer away from the substrate, at least covering a central portion of the pin, and electrically connected to the pin.

A display apparatus includes: a circuit substrate; and a pixel array on the circuit substrate and including a plurality of pixels. The pixel array includes: light emitting diode (LED) cells constituting the plurality of pixels, each of the LED cells including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer; wavelength converters on the LED cells; an upper semiconductor layer on the LED cells and having a partition structure; a passivation layer on side surfaces of the LED cells; a first electrode along a region of the LED cells to have a grid shape; second electrodes connected to the second conductivity-type semiconductor layers; and reflective layers between the first electrode and the second electrode along the passivation layer on the side surfaces of the LED cells and having surfaces inclined toward outside of the LED cells.

A light emitting diode (LED) includes a n-doped semiconductor material layer, a p-doped semiconductor material layer, an active region disposed between the n-doped semiconductor layer and the p-doped semiconductor layer, and a photonic crystal grating configured to increase the light extraction efficiency of the LED.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

The present invention provides a display device comprising: a substrate; a wiring electrode disposed on the substrate; a plurality of semiconductor light emitting elements each provided with a conductive electrode electrically connected to the wiring electrode; and an anisotropic conductive layer which is disposed between the conductive electrodes and the wiring electrode and formed of a mixture of conductive particles and an insulating material, wherein the conductive electrodes are provided with a protrusion part protruding toward the wiring electrode.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

A display device includes a plate-like substrate having a first surface and a second surface, pixel units on the first surface, and a power supply voltage feeder on the second surface. The power supply voltage feeder outputs first and second power supply voltages applicable to the pixel units. The second power supply voltage is lower in potential than the first power supply voltage. The display device includes a first wiring conductor electrically connecting the power supply voltage feeder and the pixel units and a second wiring conductor electrically connecting the power supply voltage feeder and the pixel units. At least one of the first or second wiring conductor includes a planar conductive portion covering the first surface. The planar conductive portion includes connectors connected to the power supply voltage feeder on at least two sides of the substrate.

A non-volatile memory device for performing compute in memory operations for a neural network uses a three dimensional NOR architecture in which vertical NOR strings are formed of multiple memory cells connected in parallel between a source line and a bit line. Weights of the neural network are encoded as threshold voltages of the memory cells and activations are encoded as word line voltages applied to the memory cells of the NOR strings. The memory cells are operated in the subthreshold region, where the word line voltages are below the threshold voltages. The NOR structure naturally sums the resultant subthreshold currents of the individual memory cells to generate the product of the activations and the weights of the neural network by concurrently applying input voltages to multiple memory cells of a NOR string.