H01L2224/05688

METHOD FOR CONNECTING COMPONENTS DURING PRODUCTION OF POWER ELECTRONIC MODULES OR ASSEMBLIES
20210305197 · 2021-09-30 ·

In a method for connecting components during production of power electronics modules or assemblies, surfaces of the components have a metallic surface layer upon supply, or are furnished therewith, wherein the layer has a surface that is smooth enough to allow direct bonding or is smoothed to obtain a surface that is smooth enough to allow direct bonding. The surface layers of the surfaces that are to be connected are then pressed against each other with a pressure of at least 5 MPa at elevated temperature, so that they are joined to each other, forming a single layer. The method enables simple, rapid connection of even relatively large contact surfaces, which satisfies the high requirements of power electronics modules.

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION
20210265206 · 2021-08-26 ·

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

Cu3Sn VIA METALLIZATION IN ELECTRICAL DEVICES FOR LOW-TEMPERATURE 3D-INTEGRATION
20210265206 · 2021-08-26 ·

A Cu.sub.3Sn electrical interconnect and method of making same in an electrical device, such as for hybrid bond 3D-integration of the electrical device with one or more other electrical devices. The method of forming the Cu.sub.3Sn electrical interconnect includes: depositing a Sn layer in the via hole; depositing a Cu layer atop and in contact with the Sn layer; and heating the Sn layer and the Cu layer such that the Sn and Cu layers diffuse together to form a Cu.sub.3Sn interconnect in the via hole. During the heating, a diffusion front between the Sn and Cu layers moves in a direction toward the Cu layer as initially deposited, such that any remaining Cu layer or any voids formed during the diffusion are at an upper region of the formed Cu.sub.3Sn interconnect in the via hole, thereby allowing such voids or remaining material to be easily removed.

Treatment, before the bonding of a mixed Cu-oxide surface, by a plasma containing nitrogen and hydrogen

A method for bonding a first surface provided with at least one copper area surrounded by a silicon oxide area to a second surface includes an operation of treatment of the first surface by a plasma, before placing the first surface in contact with the second surface. The plasma is formed from a gas source containing a silicon oxide nitriding agent and a copper oxide reducing agent containing hydrogen. The gas source may include an N.sub.2 and NH.sub.3 and/or H.sub.2 gas mixture or a N.sub.2O and H.sub.2 gas mixture, or ammonia, which is then used both as a nitriding agent and as a reducing agent. The plasma obtained from this gas source then necessarily contains nitrogen and hydrogen, which enables, in a single operation, to provide a high-performance bonding between the first and second surfaces.

Hybrid wafer-to-wafer bonding and methods of surface preparation for wafers comprising an aluminum metalization
10886249 · 2021-01-05 · ·

A surface treatment solution includes a fluoride source; a first solvent; and a water transforming agent to transform water produced during wafer surface treatment into a second solvent, which can be the same as, or different from, the first solvent. The solution can be used, for example, in surface preparation for wafers having a backend including an electrical interconnect that includes aluminum or an aluminum alloy.

Semiconductor devices and semiconductor devices including a redistribution layer

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Semiconductor devices and semiconductor devices including a redistribution layer

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

Method for fabricating glass substrate package
10453819 · 2019-10-22 · ·

A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES INCLUDING A REDISTRIBUTION LAYER
20190252338 · 2019-08-15 ·

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES INCLUDING A REDISTRIBUTION LAYER
20190252338 · 2019-08-15 ·

A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in a dielectric material over a substrate. The method further comprises forming a seed material at least within a bottom of the aperture and over the dielectric material, forming a protective material over the seed material within the aperture, and forming a conductive pillar in contact with the seed material through an opening in the protective material over surfaces of the seed material within the aperture. A method of forming an electrical connection between adjacent semiconductor devices, and a semiconductor device, are also described.