A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

A chip structure includes a chip substrate and a plurality of bumps. The plurality of bumps are disposed on a surface of the chip substrate and function as an interface for electrical connection between the chip substrate and an external connecting portion. The plurality of bumps are spaced apart from each other, and each of the plurality of bumps includes a rhombic configuration.

A method for bonding two superconducting integrated circuits (“chips”), such that the bonds electrically interconnect the chips. A plurality of indium-coated metallic posts may be deposited on each chip. The indium bumps are aligned and compressed with moderate pressure at a temperature at which the indium is deformable but not molten, forming fully superconducting connections between the two chips when the indium is cooled down to the superconducting state. An anti-diffusion layer may be applied below the indium bumps to block reaction with underlying layers. The method is scalable to a large number of small contacts on the wafer scale, and may be used to manufacture a multi-chip module comprising a plurality of chips on a common carrier. Superconducting classical and quantum computers and superconducting sensor arrays may be packaged.

A semiconductor device includes a semiconductor element made up of a semiconductor substrate, an element electrode formed on the substrate, and a wiring layer electrically connected to the element electrode. The semiconductor device further includes a lead frame supporting the semiconductor element, a first conductive member electrically connecting the semiconductor element and the lead frame, a second conductive member overlapping with the semiconductor element as seen in plan view, and a sealing resin covering the semiconductor element, a part of the lead frame, and the first and second conductive member. The wiring layer includes a first pad portion and a second pad portion. The second conductive member has a first connecting portion bonded to the first pad portion and a second connecting portion bonded to the second pad portion.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

Semiconductor devices can be formed over a semiconductor substrate, and interconnect-level dielectric material layers embedding metal interconnect structures can be formed thereupon. In one embodiment, a pad-connection-via-level dielectric material layer, a proximal dielectric diffusion barrier layer, and a pad-level dielectric material layer can be formed. Bonding pads surrounded by dielectric diffusion barrier portions can be formed in the pad-level dielectric material layer. In another embodiment, a layer stack of a proximal dielectric diffusion barrier layer and a pad-and-via-level dielectric material layer can be formed. Integrated pad and via cavities can be formed through the pad-and-via-level dielectric material layer, and can be filled with bonding pads containing dielectric diffusion barrier portions and integrated pad and via structures.

A terminal connection portion, which includes an IC including a plurality of input bumps and a plurality of output bumps, and a terminal connection portion including a plurality of input terminal electrodes and a plurality of output terminal electrodes, is provided in a frame region, and in the terminal connection portion, an electrode insulating film is provided on the input terminal electrodes and the output terminal electrodes. A protruding portion is provided on the electrode insulating film, and the protruding portion overlaps with the IC in a plan view, and overlaps with the input bumps and the output bumps when viewed from a direction parallel to a substrate surface of a resin substrate layer.

A terminal connection portion, which includes an IC including a plurality of input bumps and a plurality of output bumps, and a terminal connection portion including a plurality of input terminal electrodes and a plurality of output terminal electrodes, is provided in a frame region, and in the terminal connection portion, an electrode insulating film is provided on the input terminal electrodes and the output terminal electrodes. A protruding portion is provided on the electrode insulating film, and the protruding portion overlaps with the IC in a plan view, and overlaps with the input bumps and the output bumps when viewed from a direction parallel to a substrate surface of a resin substrate layer.

A semiconductor device includes a first wafer including a row decoder region in which a plurality of pass transistors are arranged in a row direction and a column direction; a plurality of first bonding pads, respectively coupled to the plurality of pass transistors that are disposed in a plurality of rows on one surface of the first wafer in the row decoder region; and a plurality of second bonding pads disposed on the one surface of the first wafer in the row decoder region, wherein the plurality of second bonding pads are disposed in a different row from the plurality of first bonding pads and are offset in the row direction with respect to the plurality of first bonding pads.

To facilitate connection with an external wiring when an electrode pad is located at a deep position from a surface of a semiconductor device. The electrode pad is formed at a predetermined depth from the surface of the substrate. A conductive portion is formed in a region from the electrode pad to the surface of the substrate. The conductive portion has a state in which it can be electrically connected to the wiring on the surface of the substrate. The conductive portion includes a wiring region for electrical connection with a wiring at a position directly above the electrode pad on the surface of the substrate or at a position different from the position directly above the electrode pad. The conductive portion can be formed by repeating a procedure of applying a conductive paste to a region from the electrode pad to the surface of the substrate and a procedure of curing the applied conductive paste.