A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9≤X.sub.2/X.sub.1≤1.0 (I), where X.sub.1 is a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and X.sub.2 is a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.

A prepreg is used to fabricate a semiconductor package including a chip and a substrate to mount the chip thereon. The prepreg is in a semi-cured state. The substrate includes a cured product of the prepreg. The chip has: a first chip surface located opposite from the substrate; and a second chip surface located opposite from the first chip surface. The prepreg satisfies the relational expression: 0.9≤X.sub.2/X.sub.1≤1.0 (I), where X.sub.1 is a coefficient of thermal expansion of the first chip surface of the chip before the chip is mounted on the substrate, and X.sub.2 is a coefficient of thermal expansion of the first chip surface of the chip after the chip has been mounted on the substrate.

A semiconductor package includes a first semiconductor die, a first substrate, a second semiconductor die, and a second substrate. The first substrate is disposed on the first semiconductor die and includes a plurality of first metal line layers vertically spaced apart from each other, and each of the first metal line layers is electrically connected to one of the followings: a ground source and a plurality of power sources of different types. The second semiconductor die is disposed on the first substrate. The second substrate is disposed on the second semiconductor die and includes a plurality of second metal line layers vertically spaced apart from each other, and each of the second metal line layers is electrically connected to one of the followings: the ground source and the power sources of different types.

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.

Techniques are provided for an inductor at a first level interface between a first die and a second die. In an example, the inductor can include a winding and a core disposed inside the winding. The winding can include first conductive traces of a first die, second conductive traces of a second die, and a plurality of connectors configured to connect the first die with the second die. Each connector of the plurality of connecters can be located between a trace of the first conductive traces and a corresponding trace of the second conductive traces.

A method for wafer bonding includes receiving a layout of a bonding layer with an asymmetric pattern, determining whether an asymmetry level of the layout is within a predetermined range by a design rule checker, modifying the layout to reduce the asymmetry level of the layout if the asymmetry level is beyond the predetermined range. The method also includes outputting the layout in a computer-readable format.

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.