Apparatuses and methods for coupling contact pads to a circuit in a semiconductor device is described. An example apparatus includes a first pad, a first wiring coupled to the first pad, a second pad, a second wiring, a circuit coupled to the second pad, and a switch circuit. The switch circuit includes first, second, and third connections, and includes first and second control gates. The first wiring is coupled to the first and third connections and second wiring is coupled to the second connection. The switch circuit is configured to couple the first wiring with the second wiring when the first and second control gates are activated and to decouple the first wiring from the second wiring when the first and second control gates are not activated.

Apparatuses and methods for coupling contact pads to a circuit in a semiconductor device is described. An example apparatus includes a first pad, a first wiring coupled to the first pad, a second pad, a second wiring, a circuit coupled to the second pad, and a switch circuit. The switch circuit includes first, second, and third connections, and includes first and second control gates. The first wiring is coupled to the first and third connections and second wiring is coupled to the second connection. The switch circuit is configured to couple the first wiring with the second wiring when the first and second control gates are activated and to decouple the first wiring from the second wiring when the first and second control gates are not activated.

Techniques of drawing ESD current away from an image sensor device of a CMOS image sensor die include using a light shield configured to block light from an image sensor device. The light shield may be used to draw the ESD current away when it has an electrical connection to an ESD ground bus and/or to a bond pad of the CMOS image sensor die. Advantageously, the light shield has a low resistance due to its large surface area. Accordingly, parallel connections to the bond pads and/or ESD bus have a resistance close to the low resistance of the light shield without altering the size of the die.

A semiconductor package includes a metallic pad and leads, a semiconductor die including a semiconductor substrate attached to the metallic pad, and a conductor including a sacrificial fuse element above the semiconductor substrate, the sacrificial fuse element being electrically coupled between one of the leads and at least one terminal of the semiconductor die, a shock-absorbing material over a profile of the sacrificial fuse element, and mold compound covering the semiconductor die, the conductor, and the shock-absorbing material, and partially covering the metallic pad and leads, with the metallic pad and the leads exposed on an outer surface of the semiconductor package. Either a glass transition temperature of the shock-absorbing material or a melting point of the shock-absorbing material is lower than a melting point of the conductor.

A fan-out structure and its manufacturing method are presented, relating to semiconductor techniques. The fan-out structure includes a welding pad; a welding pad extension member contacting the welding pad; and a fan-out line contacting the welding pad extension member, with an elicitation direction of the fan-out line perpendicular to an extension direction of the welding pad. This fan-out structure allows the fan-out line to be horizontally or vertically elicited from the welding pad, and thus remedies the drawbacks associated with an aslant-elicited fan-out line in conventional fan-out structures.

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

A method of manufacturing a semiconductor device includes depositing a first passivation layer over a substrate, depositing a conductive material over the first passivation layer, patterning the conductive material to form a redistribution layer (RDL) structure, and depositing a second passivation layer configured to change a shape of a top portion of the RDL structure.

A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.

Provided is a semiconductor package including a package substrate, a redistribution structure including a single-layered insulating layer positioned above the package substrate, and a plurality of horizontal redistribution structures embedded in the insulating layer and arranged side-by-side in a first horizontal direction parallel to an upper surface of the package substrate and in a second horizontal direction perpendicular to the first horizontal direction, external connection terminals arranged below the redistribution structure, and a semiconductor chip provided on the redistribution structure and including a chip body and chip connection terminals arranged below the chip body, wherein each of the plurality of horizontal redistribution structures includes a via passing through the insulating layer, and a tracer pattern formed integrally with the via and inclined and long from the first horizontal direction and the second horizontal direction.

A system and method for providing a post-passivation opening and undercontact metallization is provided. An embodiment comprises an opening through the post-passivation which has a first dimension longer than a second dimension, wherein the first dimension is aligned perpendicular to a chip's direction of coefficient of thermal expansion mismatch. By shaping and aligning the opening through the post-passivation layer in this fashion, the post-passivation layer helps to shield the underlying layers from stresses generated from mismatches of the materials' coefficient of thermal expansion.