Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/02
Bonding areas; Manufacturing methods related thereto
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H01L2224/04
Structure, shape, material or disposition of the bonding areas prior to the connecting process
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H01L2224/06
of a plurality of bonding areas
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H01L2224/0614
Circular array, i.e. array with radial symmetry
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H01L2224/06147
with specially adapted redistribution layers [RDL]
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H01L2224/06147

SPILT PAD FOR PACKAGE ROUTING AND ELECTRICAL PERFORMANCE IMPROVEMENT
20200111758 · 2020-04-09 ·

In conventional panel level packaging, the BGA pad itself can occupy more space on the final connection layer leaving less space to route traces and vias. To address this and other issues, connection pads such as the BGA pad can be split to allow for more efficient routing on the final connection layer.