Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

In a general aspect, a circuit includes a first ESD protection circuit having a first terminal and a second terminal, and a second ESD protection circuit having a first terminal and a second terminal. The second terminal of the second ESD protection circuit is coupled with the second terminal of the first ESD protection circuit. The circuit further includes a third ESD protection circuit having a first terminal and a second terminal. The second terminal of the third ESD protection circuit is coupled with the second terminal of the first ESD protection circuit and the second terminal of the second ESD protection circuit.

A semiconductor device 100 has a power transistor N1 of vertical structure and a temperature detection element 10a configured to detect abnormal heat generation by the power transistor N1. The power transistor N1 includes a first electrode 208 formed on a first main surface side (front surface side) of a semiconductor substrate 200, a second electrode 209 formed on a second main surface side (rear surface side) of the semiconductor substrate 200, and pads 210a-210f positioned unevenly on the first electrode 208. The temperature detection element 10a is formed at a location of the highest heat generation by the power transistor N1, the location (near the pad 210b where it is easiest for current to be concentrated) being specified using the uneven positioning of the pads 210a-210f.

A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.

Embodiments of a semiconductor packaged device and method of making thereof are provided, the device including a substrate; a first flip chip die mounted to a first major surface of the substrate; a second flip chip die mounted to the first major surface of the substrate, the second flip chip die laterally adjacent to the first flip chip die on the first major surface; and a wire bond formed between a first bond pad on the first flip chip die and a second bond pad on the second flip chip die.

A display device includes a display substrate including a display area where an image is displayed and a pad area disposed at a periphery of the display area, and a first pad portion disposed in the pad area, the first pad portion including a plurality of first line pad terminals arranged along a first curved line in a first direction.

A semiconductor device includes: a transistor provided in a first region of a semiconductor layer in a plan view; a transistor provided in a second region adjacent to the first region of the semiconductor layer in the plan view; and a drain pad provided in a third region not overlapping the first region and the second region in the plan view. In the plan view, the first region and the second region are one region and an other region that divide an area of the semiconductor layer excluding the third region in half. In the plan view, the transistors are arranged in a first direction. The center of the third region is located on a straight center line that divides the semiconductor layer in half in the first direction and is orthogonal to the first direction. In the plan view, the drain pad is contained in the third region.

The present application discloses a drive chip and a display panel. The drive chip includes a first area and a second area. The drive chip includes a substrate and drive pins. The density of the pins located in the first area is lower than the density of the pins located in the second area. The pins located in the second area includes first drive pins and second drive pins. The distance between the substrate and a face of the first drive pins away from the substrate is greater than the distance between the substrate and a face of the second drive pins away from the substrate. The occurrence of poor electric conduction is avoided.

A semiconductor device includes a semiconductor chip in a rectangular shape having longer sides extending in a first direction and shorter sides extending in a second direction. The semiconductor chip includes: a first vertical MOS transistor that includes a first gate pad and a plurality of first source pads, and a second vertical MOS transistor that includes a second gate pad and a plurality of second source pads. A plurality of first linear disposition regions in each of which source pads are linearly aligned in the first direction and a plurality of second linear disposition regions in each of which source pads are linearly aligned in the second direction are provided on an upper surface of the semiconductor chip. The semiconductor device further includes a plurality of ball-shaped bump electrodes connected to the first gate pad, the first source pads, the second gate pad, and the second source pads.

A semiconductor device includes a terminal, a first semiconductor chip, a second semiconductor chip located on the first semiconductor chip, a first pad located on the first semiconductor chip and electrically disconnected from a semiconductor circuit of the first semiconductor chip, a second pad located on the second semiconductor chip and electrically connected to a semiconductor circuit of the second semiconductor chip, a first wire electrically connecting the first terminal to the first pad, and a second wire electrically connecting the first pad to the second pad..