A semiconductor device includes a first electronic component, a second electronic component and a plurality of interconnection structures. The first electronic component has a first surface. The second electronic component is over the first electronic component, and the second electronic component has a second surface facing the first surface of the first electronic component. The interconnection structures are between and electrically connected to the first electronic component and the second electronic component, wherein each of the interconnection structures has a length along a first direction substantially parallel to the first surface and the second surface, a width along a second direction substantially parallel to the first surface and the second surface and substantially perpendicular to the first direction, and the length is larger than the width of at least one of the interconnection structures.

A semiconductor package includes: (1) a substrate; (2) a first isolation layer disposed on the substrate, the first isolation layer including an opening; (3) a pad disposed on the substrate and exposed from the opening; (4) an interconnection layer disposed on the pad; and (5) a conductive post including a bottom surface, the bottom surface having a first part disposed on the interconnection layer and a plurality of second parts disposed on the first isolation layer.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having a mixed under-bump metallization (UBM) size and pitch on a single die. A first set of UBMs having a first total plateable surface area is formed on a first region of a die. A second set of UBMs having an equal total plateable surface area is formed on a second region of the die. A solder bump having a calculated solder height is applied to a plateable surface of each UBM. The solder height is calculated such that a volume of solder in the first region is equal to a volume of solder in the second region.

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground.

A board unit according to an embodiment includes a circuit board, a semiconductor device, and a wire. The semiconductor device has a bottom surface facing the circuit board. The semiconductor device includes a plurality of bonding members between the circuit board and the bottom surface. The wire is disposed between the circuit board and the bottom surface. The bonding members have a first row and a second row. Two or more bonding members align in the first row in a first direction. Two or more bonding members align in the second row in the first direction. The second row is apart from the first row in a second direction intersecting with the first direction. The wire includes a first portion disposed between the first row and the second row, and the wire has a strength higher than that of one of the bonding members.

A device comprising an integrated device. The integrated device comprising a die substrate; an interconnect portion coupled to the die substrate, a plurality of pillar interconnects and a passivation layer coupled to the interconnect portion. The interconnect portion includes a first plurality of pads and a second plurality of pads. The first plurality of pads are configured to provide a first plurality of electrical paths for input/output signals. The second plurality of pads are configured to provide a second plurality of electrical paths for power. The plurality of pillar interconnects are coupled to the first plurality of pads and the second plurality of pads. The passivation layer comprises a plurality of openings. The plurality of openings include at least one opening located over a pad from the first plurality of pads.

An analog time delay filter circuit including a first delay circuit block arranged in a modular layout, having a first time delay filter, a first input, a first output, and first and second pass-throughs; and a second delay circuit block arranged in the same modular layout, having a second time delay filter, a second input, a second output, and third and fourth pass-throughs.

A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

A surface mounting semiconductor component includes a semiconductor device, a circuit board, a number of first solder bumps, and a number of second solder bumps. The semiconductor device included a number of die pads. The circuit board includes a number of contact pads. The first solder bumps are configured to bond the semiconductor device and the circuit board. Each of the first solder bumps connects at least two die pads with a corresponding contact pad. Each of the second solder bumps connects a die pad with a corresponding contact pad.