Patent classifications
H01L2224/13552
Semiconductor chip having stepped conductive pillars
In an implementation, a semiconductor chip includes a device layer, an interconnect layer fabricated on the device layer, the interconnect layer including a conductive pad, and a conductive pillar coupled to the conductive pad. The conductive pillar includes at least a first portion having a first width and a second portion having a second width, the first portion being disposed between the second portion and the conductive pad, wherein the first width of the first portion is greater than the second width of the second portion.
Copper pillar bump structure and method of manufacturing the same
A copper pillar bump (CPB) structure is provided in the present invention, including a substrate, a pad on the substrate, a passivation layer covering the substrate and exposing the pad, and a copper pillar on the passivation layer and the pad and connecting directly with the pad. The copper pillar is provided with an upper part and a lower part, and a top surface of the lower part includes a first top surface and a second top surface. The second top surface is on one side of the first top surface, and the upper part of the copper pillar is on the first top surface of the lower part. A metal bump is on the copper pillar, wherein parts of the metal bump directly contact the second top surface of the lower part.
ELECTRONIC COMPONENT, HIGH-FREQUENCY MODULE, AND COMMUNICATION DEVICE
An electronic component includes a substrate and a pillar electrode. The substrate includes a first principal surface. The pillar electrode protrudes from the first principal surface of the substrate in a thickness direction of the substrate. The pillar electrode is positioned between the first principal surface of the substrate and a bump electrode. The pillar electrode includes a second principal surface and a peripheral surface. The second principal surface is in contact with the bump electrode. The peripheral surface is connected to the second principal surface and to the first principal surface of the substrate. The pillar electrode includes a groove disposed at the second principal surface of the pillar electrode. A bottom of the groove is connected to the peripheral surface of the pillar electrode.