Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

An image pickup module includes a plurality of semiconductor devices laminated via a sealing layer a signal is transmitted via a signal cable connected to a rear surface of the image pickup module, a first semiconductor device has a semiconductor circuit portion in a central area on a first principal plane, through wires in an intermediate area and first electrodes connected to the through wires in the central area on a second principal plane, the second semiconductor device has second electrodes in the central area on a third principal plane, and an external connection terminal to which the signal cable is connected, on a rear surface, and the sealing layer includes a first sealing layer arranged in the central area and a second sealing layer disposed in an outer circumferential area surrounding the intermediate area and with a Young's modulus smaller than a Young's modulus of the first sealing layer.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

An image pickup module includes a plurality of semiconductor devices laminated via a sealing layer a signal is transmitted via a signal cable connected to a rear surface of the image pickup module, a first semiconductor device has a semiconductor circuit portion in a central area on a first principal plane, through wires in an intermediate area and first electrodes connected to the through wires in the central area on a second principal plane, the second semiconductor device has second electrodes in the central area on a third principal plane, and an external connection terminal to which the signal cable is connected, on a rear surface, and the sealing layer includes a first sealing layer arranged in the central area and a second sealing layer disposed in an outer circumferential area surrounding the intermediate area and with a Young's modulus smaller than a Young's modulus of the first sealing layer.

In an embodiment, a method for forming a solder bump includes preparing a transfer mold having a solder pillar extending from a mold substrate and through a first photoresist layer and having a shape partially defined by a second photoresist layer that is removed prior to transfer of the solder. In an embodiment, the mold substrate is flexible. In an embodiment, the transfer mold is flexible. In an embodiment, the method includes providing a device substrate having a wettable pad. In an embodiment, the method includes placing the transfer mold and the device substrate into aligned contact such that the solder pillar is in contact with the wettable pad. In an embodiment, the method includes forming a metallic bond between the solder pillar and the wettable pad. In an embodiment, the method includes removing the mold substrate and first photoresist layer.

The disclosed technology is directed to an imaging module of an endoscope comprises a plurality of semiconductor devices includes first and second semiconductor devices being electrically stacked to one another with a sealing layer interposed therebetween to transmit signals via a signal cable connected to a rear wall of the plurality of semiconductor devices. The first semiconductor device includes respective opposed first and second major surfaces having a first central region. The first major surface includes a semiconductor circuit portion disposed in the central region thereof. A through-silicon via is disposed in an intermediate region surrounding the first central region and is connected to the semiconductor circuit portion. The second major surface includes a first electrode located in the first central region thereof. The first electrode is connected to the through-silicon via. The second semiconductor device includes respective opposed third and fourth major surfaces having a second central region.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.