Within a layout of a first surface in a flip chip configuration, a bump restriction area is mapped according to a set of bump placement restrictions, wherein a first bump placement restriction specifies an allowed distance range between a bump and a qubit chip element in a layout of the first surface in the flip chip configuration. An electrically conductive material is deposited outside the bump restriction area, to form the bump, wherein the bump comprises an electrically conductive structure that electrically couples a signal from the first surface and is positioned according to the set of bump placement restrictions.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.

A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.

A semiconductor device includes a semiconductor layer that has a main surface, a trench gate structure that includes a trench formed in the main surface and having a first sidewall at one side, a second sidewall at the other side and a bottom wall in a cross-sectional view, an insulation layer formed on an inner wall of the trench, and a gate electrode embedded in the trench with the insulation layer between the trench and the gate electrode and having an upper end portion positioned at a bottom-wall side with respect to the main surface, a plurality of first-conductivity-type drift regions that are respectively formed in a region at the first sidewall side of the trench and in a region at the second sidewall side of the trench such as to face each other with the trench interposed therebetween in a surface layer portion of the main surface and that are positioned in a region at the main surface side with respect to the bottom wall, and a plurality of first-conductivity-type source/drain regions that are formed in surface layer portions of the plurality of drift regions, respectively.

A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.

A driving chip and a display device are provided herein. The driving chip includes a substrate, a plurality of connection bumps and a plurality of buffer bumps on the substrate. Each of the connection bumps and the buffer bumps is disposed on a first substrate of the substrate. The buffer bump includes a first end face with a height a, and the connection bump has a connection bump end face with a height b, a<b. The height is a distance from a corresponding end face of the connection bump or the buffer bump to the first surface. With the buffer bumps on the driving chip, stress buffering can be achieved, which can further improve the bonding effect of the driving chip.

A power amplifier device includes a semiconductor substrate; a plurality of first transistors that are provided on the semiconductor substrate and receive input of a radio-frequency signal; a plurality of second transistors that are provided on the semiconductor substrate and electrically connected to the respective plurality of first transistors, and output a radio-frequency output signal obtained by amplifying the radio-frequency signal; a plurality of first bumps provided so as to overlay the respective plurality of first transistors; and a second bump provided away from the plurality of first bumps and provided so as not to overlay the plurality of first transistors and the plurality of second transistors. When viewed in plan from a direction perpendicular to a surface of the semiconductor substrate, a first transistor and a first bump, a second transistor, the second bump, a second transistor, and a first transistor and a first bump are arranged in sequence.

The display device includes a flexible base layer including a first region and a second region located around the first; a display unit on one surface of the first region and including a light emitting element; a driving circuit on the second region and including a plurality of first bumps arranged in a first row and a plurality of second bumps arranged in a second row, the driving circuit includes a third bump in the first row and disposed outward relative to the plurality of first bumps, a first and second reference bump each disposed at a center of the plurality of first and second bumps that are disposed along a reference line defined in a column direction vertically intersecting a row direction, the remaining first and second bumps excluding the first reference bump and the second reference bump arranged to have a preset slope with respect to the reference line.

Millimeter wave (mmWave) technology, apparatuses, and methods that relate to transceivers, receivers, and antenna structures for wireless communications are described. The various aspects include co-located millimeter wave (mmWave) and near-field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication system with MIMO support and phase noise synchronization over a single coax cable, communicating RF signals over cable (RFoC) in a distributed phased array communication system, clock noise leakage reduction, IF-to-RF companion chip for backwards and forwards compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architecture, among others.

A semiconductor device assembly that includes a substrate having a first side and a second side, the first side having at least one dummy pad and at least one electrical pad. The semiconductor device assembly includes a first semiconductor device having a first side and a second side and at least one electrical pillar extending from the second side. The electrical pillar is connected to the electrical pad via solder to form an electrical interconnect. The semiconductor device assembly includes at least one dummy pillar extending from the second side of the first semiconductor device and a liquid positioned between an end of the dummy pillar and the dummy pad. The surface tension of the liquid pulls the dummy pillar towards the dummy pad. The surface tension may reduce or minimize a warpage of the semiconductor device assembly and/or align the dummy pillar and the dummy pad.