A package comprising a package substrate; a first integrated device coupled to the package substrate through a first plurality of solder interconnects; an encapsulation layer at least partially encapsulating the first integrated device; a plurality of post interconnects located in the encapsulation layer; a metallization portion coupled to the plurality of post interconnects; a second integrated device coupled to the metallization portion through a second plurality of solder interconnects; an optical integrated device coupled to the package substrate; and an optical fiber coupled to the optical integrated device.

A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.

A semiconductor package device includes a substrate, a passive component, an active component and a package body. The passive component is disposed on the substrate. The active component is disposed on the substrate. The package body is disposed on the substrate. The package body includes a first portion covering the active component and the passive component, and a second portion covering the passive component. A top surface of the second portion of the package body is higher than a top surface of the first portion of the package body.

A package structure includes a substrate having an upper surface; a first chip package positioned on the upper surface of the substrate, the first chip package comprising a first chip having a first integrated circuit connected to a first redistribution layer; a second chip package positioned on the upper surface of the substrate, the second chip package comprising a second chip having a second integrated circuit connected to a second redistribution layer; an orthogonal bridge positioned between the first chip package and the second chip package and having an interconnection to the first redistribution layer and the second redistribution layer; and a heat spreader positioned in direct contact with at least one of the first chip package, the second chip package, or the orthogonal bridge. The orthogonal bridge is arranged substantially orthogonal to the upper surface of the substrate.

A circuit package is described that includes a photonic interposer, a second interposer, and a die partially overlapping and connected to both the photonic interposer and the second interposer.

A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a first dielectric over the semiconductor substrate. The semiconductor device also includes a conductive layer disposed in the first dielectric and a second dielectric disposed on the conductive layer. In the semiconductor device, at least a portion of the conductive layer is exposed from the first dielectric and second dielectric. The semiconductor device further includes a conductive trace partially over the second dielectric and in contact with the exposed portion of the conductive layer. In the semiconductor device, the conductive trace is connected to the conductive pad at one end.

A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more projections extending from the pads are shown where the projections occupy only a fraction of a surface area of the pads. Processes such as thermal compression bonding using solder pads as described are also shown.

An electronic device includes (i) an integrated circuit (IC) die mounted on a substrate, (ii) a lid having first and second surfaces facing one another, and one or more openings formed through the lid between the first and second surfaces, the lid being disposed over at least the IC die to form a space between the IC die and the first surface of the lid, the one or more openings are configured to enable transference of fluids through the lid, (iii) a liquid thermal interface material (TIM) filling the space and being formulated to conduct heat from the IC die to the lid, and (iv) a stopper structure extended from the first surface of the lid, the stopper structure includes one or more sidewalls configured to contain the liquid TIM at least in the space between the IC die and the first surface of the lid.

A package structure includes a package substrate, a system on a chip (SoC), at least one input/output circuit, multiple optoelectronic assemblies and an organic interposer. The SoC is disposed on the package substrate and includes a central processing unit (CPU), a graphics processing unit (GPU) and a memory. The input/output circuit is disposed on the package substrate. The optoelectronic assemblies are separately disposed on the package substrate and surround the SoC and the input/output circuit. The organic interposer is disposed on the package substrate. The SoC, the input/output circuit and the optoelectronic assemblies are electrically connected to the package substrate through the organic interposers.