A semiconductor package structure includes at least one first semiconductor die, at least one second semiconductor die and an encapsulant. The first semiconductor die has a first surface and includes a plurality of first pillar structures disposed adjacent to the first surface. The second semiconductor die is electrically connected to the first semiconductor die. The encapsulant covers the first semiconductor die and the second semiconductor die. A lower surface of the encapsulant is substantially coplanar with an end surface of each of the first pillar structures and a surface of the second semiconductor die.

A semiconductor device package having galvanic isolation is provided. The semiconductor device includes a package substrate having a first inductive coil formed from a first conductive layer and a second inductive coil formed from a second conductive layer. The first conductive layer and the second conductive layer are separated by a non-conductive material. A first semiconductor die is attached to a first major side of the package substrate. The first semiconductor die is conductively interconnected to the first inductive coil. A second semiconductor die is attached to the first major side of the package substrate. A first wireless communication link between the first semiconductor die and the second semiconductor die is formed by way of the first and second inductive coils.

A semiconductor device includes a first die, a second die on the first die, and a third die on the second die, the second die being interposed between the first die and the third die. The first die includes a first substrate and a first interconnect structure on an active side of the first substrate. The second die includes a second substrate, a second interconnect structure on a backside of the second substrate, and a power distribution network (PDN) structure on the second interconnect structure such that the second interconnect structure is interposed between the PDN structure and the second substrate.

A semiconductor device, and method of making the same, comprising a plurality of conductive studs formed over an active surface of a semiconductor die. The plurality of conductive studs may be disposed around a device mount site, wherein the device mount site comprises conductive interconnects comprising a height less than a height of the plurality of conductive studs. An encapsulant may be disposed around the semiconductor die and the conductive studs. A portion of the conductive studs may be exposed from the encapsulant at a planar surface. A build-up interconnect structure comprising one or more layers may be disposed over and coupled to the planar surface, the conductive studs, and the conductive interconnect. A device may be coupled to the conductive interconnects of the device mount site.

A system that includes multiple integrated circuits is disclosed. A first integrated circuit of the system includes a plurality of circuit blocks, and a first circuit block of the plurality of circuit blocks includes a first power terminal. A second integrated circuit of the system includes multiple voltage regulation circuits, a second power terminal coupled to an output of a given voltage regulation circuit, and a third power terminal coupled to an input of the given voltage regulation circuit. A substrate, included in the system, includes a plurality of conductive paths, each of which includes a plurality of wires fabricated on a plurality of conductive layers. The system further includes a power management unit that may be configured to generate a power supply voltage at a fourth power terminal that is coupled to the third power terminal via a first conductive path of the plurality of conductive paths.

A semiconductor package includes a package substrate including a first region, a thermal block penetrating the first region and exposed at top and bottom surfaces of the package substrate, a semiconductor chip on the package substrate, bumps disposed between the package substrate and the semiconductor chip and including first bumps being in contact with the thermal block, and terminals disposed on the bottom surface of the package substrate and including first terminals being in contact with the thermal block. The thermal block is one of a power path and a ground path.

Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

A magnetic polymer for use in microelectronic fabrication includes a polymer matrix and a plurality of ferromagnetic particles disposed in the polymer matrix. The magnetic polymer can be part of an insulation layer in an inductor formed in one or more backend wiring layers of an integrated device. The magnetic polymer can also be in the form of a magnetic epoxy layer for mounting contacts of the integrated device to a package substrate.

A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).