A semiconductor device and an amplifier assembly implementing the semiconductor device are disclosed. The semiconductor device, which is a type of Doherty amplifier, includes first transistor elements for a carrier amplifier of the Doherty amplifier and second transistor elements for a peak amplifier. A feature of the Doherty amplifier is that the first transistor elements and the second transistor elements are disposed alternatively on a common semiconductor substrate.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

An electronic component includes: four device chips having rectangular planar shapes and arranged on a substrate so that a corner of four corners constituting a rectangle of one device chip is adjacent to the corners of remaining three device chips; first pads located on surfaces of the four device chips and closest to the corner; one or more first bumps bonding the first pads to the substrate in the four device chips; second pads located on surfaces of the four device chips, the second pad being one of pads other than the first pad; and one or more second bumps bonding the second pads to the substrate in the four device chips, a sum of bonded areas between the one or more second bumps and the second pad being less than a sum of bonded areas between the first pad and the one or more first bumps.

Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

Semiconductor die assemblies having interconnect structures with redundant electrical connectors are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die, a second semiconductor die, and an interconnect structure between the first and the second semiconductor dies. The interconnect structure includes a first conductive film coupled to the first semiconductor die and a second conductive film coupled to the second semiconductor die. The interconnect structure further includes a plurality of redundant electrical connectors extending between the first and second conductive films and electrically coupled to one another via the first conductive film.

A method of manufacturing an electronic component module and the electronic component module manufactured by the manufacturing method includes bumps, each including a thicker portion having a relatively large thickness and a thinner portion having a relatively small thickness and formed on one surface of the substrate. When looking at the electronic component in a mounted state in a plan view, the thicker portion is positioned on a side of a corresponding outer terminal closer to a center of the electronic component and the thinner portion is positioned on the opposite side of the corresponding outer terminal. In the plan view, joining portions joining the outer terminals respectively to the bumps are formed such that a height of each joining portion on the opposite side is lower than a height of the joining portion on the side closer to the center of the electronic component.

An electronic device includes a first semiconductor die, a plurality of bumps, and a substrate. The first semiconductor die includes a first conductive feature. The bumps are disposed on the first semiconductor die and are connected to the first conductive feature. The substrate includes a second conductive feature. The bumps are electrically connected to the second conductive feature. The first conductive feature, the bumps, and the second conductive feature are configured to form at least one ring structure.

A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.

A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.

A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.