A transmission line (12) includes a multilayer substrate (20), a signal pattern line (30), a ground pattern conductor (50), and an intermediate ground pattern conductor (40) that is arranged between the signal pattern line (30) and the ground pattern conductor (50) and that is electrically connected to the ground pattern conductor (50). The signal pattern line (30) has a first connection point (30c) to which a signal conductor extending in a laminating direction of the multilayer substrate (20) is connected. A first cavity portion (41h) is formed in the intermediate ground pattern conductor (40) at a position overlapped with a first end portion (30a) of the signal pattern line (30) in a plan view of the multilayer substrate (20). A first end edge (41e) of the first cavity portion (41h) has a first overlapping portion (41a) overlapped with the signal pattern line (30).

The present disclosure relates to a die comprising metal pillars extending from a surface of the die, the height of each pillar being substantially equal to or greater than 20 μm, the pillars being intended to raise the die when fastening the die by means of a bonding material on a surface of a support. The metal pillars being inserted into the bonding material at which point the bonding material is annealed to be cured and hardened solidifying the bonding material to couple the die to the surface of the support.

A semiconductor chip includes a chip pad arranged at a surface of the semiconductor chip. A dielectric layer is arranged at the surface of the semiconductor chip. The dielectric layer has an opening within which a contact portion of the chip pad is exposed, the opening having at least one straight side. The dielectric layer includes a solder flux outgassing trench arranged separate from and in the vicinity of the at least one straight side of the opening and that extends laterally beyond sides of the opening adjoining the straight side.

RF transistor amplifiers include a Group III nitride-based RF transistor amplifier die that includes a semiconductor layer structure, a conductive source via that is connected to a source region of the Group III nitride-based RF transistor amplifier die, the conductive source via extending through the semiconductor layer structure, and an additional conductive via that extends through the semiconductor layer structure. A first end of the additional conductive via is connected to a first external circuit and a second end of the additional conductive via that is opposite the first end is connected to a first matching circuit.

A transistor amplifier includes a group III-nitride based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die and an interconnect structure electrically bonded to the gate terminal, drain terminal and source terminal of the amplifier die on the first surface of the amplifier die and electrically bonded to an input path and output path of the transistor amplifier.

A semiconductor device assembly has a first substrate, a second substrate, and an anisotropic conductive film. The first substrate includes a first plurality of connectors. The second substrate includes a second plurality of connectors. The anisotropic conductive film is positioned between the first plurality of connectors and the second plurality of connectors. The anisotropic conductive film has an electrically insulative material and a plurality of interconnects laterally separated by the electrically insulative material. The plurality of interconnects forms electrically conductive channels extending from the first plurality of connectors to the second plurality of connectors. A method includes connecting the plurality of interconnects to the first plurality of connectors and the second plurality of connectors, such that the electrically conductive channels are operable to conduct electricity from the first substrate to the second substrate. The method may include passing electrical current through the plurality of interconnects.

A transistor amplifier includes a semiconductor layer structure comprising first and second major surfaces and a plurality of unit cell transistors on the first major surface that are electrically connected in parallel, each unit cell transistor comprising a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure is free of a via to the source fingers on the second major surface.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A package structure includes a first encapsulation member, a second encapsulation member, at least one semiconductor chip, a plurality of metal pins and a second insulation layer. The first encapsulation member includes a first metal layer, a first insulation layer and a second metal layer. The at least one semiconductor chip is disposed between the first encapsulation member and the second encapsulation member. The at least one semiconductor chip comprises a plurality of conductive terminals connected with the first metal layer or a third metal layer. The plurality of metal pins are disposed between and extended outward from the first encapsulation member and the second encapsulation member. The second insulation layer is disposed between the first encapsulation member and the second encapsulation layer for securing the first encapsulation member, the second encapsulation member, the at least one semiconductor chip, and the plurality of metal pins.

Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.