A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.

This invention provides a placement area with an enlarged bump pitch while avoiding the risk of underfill void generation in the bump process.

The number of bumps is not changed, but the bump pitch at the center is arranged in parallel with the drying direction of the flip-chip process in the drying direction, and an arrangement area in which n rows are enlarged by +b(m) bump pitch is made, and the chip area is finely adjusted.

According to the invention, with respect to the dry air direction after flux cleaning, the power of the dry air does not change for creating a minute bump enlarged area parallel to the air in the central portion.

A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction X and a plurality of sub-wiring units extending in a direction Y, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction X and a plurality of sub-wiring units extending in the direction Y, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction X between the main wiring units. To the end units, via wirings are coupled.

A semiconductor package, including a substrate extending in first direction and a second direction intersecting the first direction and including a solder resist layer having an open area thereon; a semiconductor chip on the substrate in a third direction, the third direction intersecting the first direction and the second direction, a first surface of the semiconductor chip facing the substrate; and a bump structure in contact with a first connection pad on the open area and a second connection pad on the first surface of the semiconductor chip, and configured to connect the substrate to the semiconductor chip, wherein the open area includes a first area and a second area disposed in a peripheral part of the first area, and wherein a length of the first area in the first direction is greater than a length of the second area in the first direction.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.

A chip on film package includes: a base substrate having an output pad region; a plurality of output pads disposed in the output pad region of the base substrate, wherein the output pads are arranged in a zigzag configuration on the base substrate; a plurality of output pad wirings connected to the output pads, respectively; and a protection layer disposed on the output pad wirings. The protection layer is disposed on the output pad wirings disposed between two adjacent output pads, arranged in a first direction.

In examples, a semiconductor package comprises a semiconductor die having a device side comprising circuitry formed therein; a passivation layer abutting the device side; first and second horizontal metal members coupled to the device side by way of vias extending through the passivation layer, the first and second horizontal metal members having thicknesses ranging from 4 microns to 25 microns; first and second metal posts coupled to and vertically aligned with the first and second metal members, respectively, the first and second metal posts having vertical thicknesses ranging from 10 microns to 80 microns; first and second solder bumps coupled to the first and second metal posts, respectively; and a ball grid array (BGA) substrate coupled to the first and second solder bumps. The BGA substrate comprises a substrate member; first and second horizontal top metal members abutting the substrate and coupled to the first and second solder bumps, respectively; first and second vias coupled to the first and second horizontal top metal members and extending through the substrate member; and first and second horizontal bottom metal members abutting the substrate and coupled to the first and second vias, respectively. The first horizontal top metal member, the first via, and the first horizontal bottom metal member are electrically coupled to a signal terminal of the semiconductor die and are configured to provide signal currents. The second horizontal top metal member, the second via, and the second horizontal bottom metal member are electrically coupled to a power terminal of the semiconductor die and are configured to provide power currents.

A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.

A semiconductor package includes a substrate having a top surface on which a semiconductor chip is mounted and a bottom surface opposite the top surface, an upper metal pattern including an upper connection region to which an external electrical device is connected and a chip connection region to which the semiconductor chip is connected, a lower metal pattern including a lower connection region to which other external electrical device is connected, and an intermediate metal pattern electrically connecting the upper and lower metal patterns. The upper metal pattern provides at least three groups of inner leads. The lower metal pattern provides at least three groups of outer leads. A module, such as that of a display device, may include the semiconductor package.