Disclosed are techniques for integrated circuits (ICs). In an aspect, an IC package includes a package substrate having an upper surface, a lower surface, a first side, and a second side perpendicular to the first side. The package substrate includes a metallization structure. The IC package further includes an IC die attached to the upper surface of the package substrate; first package bumps on the lower surface of the package substrate; and second package bumps on the lower surface of the package substrate. The first package bumps are arranged adjacent to one another along a diagonal direction that is diagonal to the package substrate, and the second package bumps are arranged adjacent to one another along the diagonal direction.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.

An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.

A semiconductor device has a wiring substrate on which a semiconductor chip is mounted. A wiring layer of the wiring substrate has a wiring. This wiring has a main wiring unit extending in a direction X and a plurality of sub-wiring units extending in a direction Y, in a cross sectional view, and is supplied with a power source potential. The wiring layer has a wiring. This wiring has a main wiring unit extending in the direction X and a plurality of sub-wiring units extending in the direction Y, in a cross sectional view, and is supplied with a reference potential. The sub-wiring units and the sub-wiring units have end units and end units on a side opposed to the end units, and are alternately arranged along the direction X between the main wiring units. To the end units, via wirings are coupled.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.

A semiconductor package may include vertically-stacked semiconductor chips and first, second, and third connection terminals connecting the semiconductor chips to each other. Each of the semiconductor chips may include a semiconductor substrate, an interconnection layer on the semiconductor substrate, penetration electrodes connected to the interconnection layer through the semiconductor substrate, and first, second, and third groups on the interconnection layer. The interconnection layer may include an insulating layer and first and second metal layers in the insulating layer. The first and second groups may be in contact with the second metal layer, and the third group may be spaced apart from the second metal layer. Each of the first and third groups may include pads connected to a corresponding one of the first and third connection terminals in a many-to-one manner. The second group may include pads connected to the second connection terminal in a one-to-one manner.

A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.