A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.

An electronic device includes a substrate, a plurality of micro semiconductor structure, a plurality of conductive members, and a non-conductive portion. The substrate has a first surface and a second surface opposite to each other. The micro semiconductor structures are distributed on the first surface of the substrate. The conductive members electrically connect the micro semiconductor structures to the substrate. Each conductive member is defined by an electrode of one of the micro semiconductor structures and a corresponding conductive pad on the substrate. The non-conductive portion is arranged on the first surface of the substrate. The non-conductive portion includes one or more non-conductive members, and the one or more non-conductive members are attached to the corresponding one or more conductive members of the one or more micro conductive structures.

A chip package structure and a method for forming a chip package are provided. The chip package structure includes a chip package over a printed circuit board and multiple conductive bumps between the chip package and the printed circuit board. The chip package structure also includes one or more thermal conductive elements between the chip package and the printed circuit board. The thermal conductive element has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps.

A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.

In examples, a semiconductor package comprises a substrate having multiple conductive layers coupled to bond pads at a surface of the substrate. The package includes a semiconductor die including a device side facing the substrate, the device side having first and second circuitry regions, the first circuitry region having greater sensitivity to at least one of mechanical or thermal stress than the second circuitry region. The package also includes conductive members coupled to the bond pads of the substrate, in direct physical contact with the second circuitry region, and not in direct physical contact with the first circuitry region. The package further comprises a first support member coupled to the device side of the semiconductor die and extending toward the substrate and not touching the substrate or a second support member coupled to the substrate. The package also includes a ring on the substrate and encircling the bond pads and a glob top member covering the semiconductor die and a portion of the substrate circumscribed by the ring. The package also includes a mold compound covering the glob top member and the substrate.

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

An electronic device includes: a first circuit board; a second circuit board located above a first region of the first circuit board; a first semiconductor element located above a second region of the first circuit board, which is different from the first region, and above a third region of the second circuit board; a first connection interposed between the first semiconductor element and the second region so as to electrically interconnect the first semiconductor element and the first circuit board; and a second connection interposed between the first semiconductor element and the third region so as to electrically interconnect the first semiconductor element and the second circuit board.

A semiconductor package includes: a semiconductor integrated circuit; an interlayer film disposed on the semiconductor integrated circuit; a rewiring layer disposed on the interlayer film; post electrodes disposed on the rewiring layer; a protective layer which is disposed on the interlayer film and covers the rewiring layer and the post electrodes; and a plurality of balls which is respectively disposed on the post electrodes and is connected to the rewiring layer, wherein balls existing on a wiring path of internal wirings connected to inner lands of a plurality of lands, which is arranged on a printed circuit board substrate to face the plurality of balls and is connectable to the plurality of balls, are non-connected to the rewiring layer.

A packaged IC includes a fanout layer, an Application Processor (AP) die having a first surface residing substantially adjacent a first surface of the fanout layer, a Redistribution Layer (RDL) having a first surface coupled to a second surface of the AP die Process, and high bandwidth memory coupled to a second surface of the RDL and configured to communicate wirelessly with the AP die. The packaged IC further includes an encapsulant surrounding a substantial portion of the high bandwidth memory, the RDL, and the AP die, the encapsulant contacting the fanout layer on a first side and having an exposed second side, a plurality of conductive posts extending from the fanout layer to the RDL through a portion of the encapsulant, and a plurality of Through Mold Vias (TMVs) extending between the fanout layer and the exposed second side of the encapsulant.

A memory device including an interposer including a first plurality of paths and a second plurality of paths, a first memory die attached to a first surface of the interposer, the first memory die including a first physical layer connected to the first plurality of paths, the first physical layer being attached to a first surface of the interposer, and a second memory die attached to a second surface of the interposer, the second memory die including a second physical layer connected to the second plurality of paths, the second physical layer being attached to a second surface of the interposer, the second physical layer not interfering with the first physical layer in a plan view may be provided.