A leadless packaged semiconductor device includes a metal substrate having at least a first through-hole aperture having a first outer ring and a plurality of cuts through the metal substrate to define spaced apart metal pads on at least two sides of the first through-hole aperture. A semiconductor die that has a back side metal (BSM) layer on its bottom side and a top side with circuitry coupled to bond pads is mounted top side up on the first outer ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate bounding the first through-hole aperture that provides a die attachment that fills a bottom portion of the first through-hole aperture. Bond wires are between metal pads and the bond pads. A mold compound is also provided including between adjacent ones of the metal pads.

A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising one or more conductive shielding members and an EMI shielding layer, and a method of manufacturing thereof.

A package structure including a lead frame structure, a die, an adhesive layer, and at least one three-dimensional (3D) printing conductive wire is provided. The lead frame structure includes a carrier and a lead frame. The carrier has a recess. The lead frame is disposed on the carrier. The die is disposed in the recess. The die includes at least one pad. The adhesive layer is disposed between a bottom surface of the die and the carrier and between a sidewall of the die and the carrier. The 3D printing conductive wire is disposed on the lead frame, the adhesive layer, and the pad, and is electrically connected between the lead frame and the pad.

An integrated circuit device package includes a substrate, a first die comprising active electronic components attached to the substrate, and package leads configured to conduct electrical signals between the first die and an external device. At least one integrated interconnect structure is provided on the first die opposite the substrate. The at least one integrated interconnect structure extends from the first die to an adjacent die attached to the substrate and/or to at least one of the package leads, and provides electrical connection therebetween. Related devices and power amplifier circuits are also discussed.

A fingerprint identification chip package of reduced thickness in not requiring a supporting substrate includes a packaging material layer, a fingerprint identification chip in the packaging material layer, conductive pillars in the packaging material layer for structural support, the pillars being spaced apart from the fingerprint identification chip, and a redistribution layer on a side of the packaging material layer. The redistribution layer includes connecting wires, each wire is electrically coupled between the fingerprint identification chip and one conductive pillar. A plurality of pins is on a side of the packaging material layer opposite to the redistribution layer, each pin is electrically coupled to one conductive pillar.

A method of manufacturing semiconductor devices such as integrated circuits comprises: providing one or more semiconductor chips having first and second opposed surfaces, coupling the semiconductor chip or chips with a support substrate with the second surface towards the support substrate, embedding the semiconductor chip or chips coupled with the support substrate in electrically-insulating packaging material by providing in the packaging material electrically-conductive passageways. The electrically-conductive passageways comprise: electrically-conductive chip passageways towards the first surface of the at least one semiconductor chip, and/or electrically-conductive substrate passageways towards the support substrate.

In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

A method comprises molding laser direct structuring material onto at least one semiconductor die, forming resist material on the laser direct structuring material, producing mutually aligned patterns of electrically-conductive formations in the laser direct structuring material and etched-out portions of the resist material having lateral walls sidewise of said electrically-conductive formations via laser beam energy, and forming electrically-conductive material at said etched-out portions of the resist material, the electrically-conductive material having lateral confinement surfaces at said lateral walls of said etched-out portions of the resist material.

Disclosed herein is a method, including attaching a semiconductor chip to a chip mounting portion on at least one leadframe portion, and attaching a passive component on a passive component mounting portion of the at least one leadframe portion. The method further includes forming a laser direct structuring (LDS) activatable molding material over the semiconductor chip, passive component, and the at least one leadframe portion. Desired patterns of structured areas are formed within the LDS activatable molding material by activating the LDS activatable molding material. The desired patterns of structured areas are metallized to form conductive areas within the LDS activatable molding material to thereby form electrical connection between the semiconductor chip and the passive component. A passivation layer is formed on the LDS activatable molding material.