The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

An advanced through silicon via structure for is described. The device includes a substrate including integrated circuit devices. A high aspect ratio through substrate via is disposed in the substrate. The through substrate via has vertical sidewalls and a horizontal bottom. The substrate has a horizontal field area surrounding the through substrate via. A metallic barrier layer is disposed on the sidewalls of the through substrate via. A surface portion of the metallic barrier layer has been converted to a nitride surface layer by a nitridation process. The nitride surface layer enhances the nucleation of subsequent depositions. A first metal layer fills the through substrate via and has a recess in an upper portion. A second barrier layer is disposed over the recess. A second metal layer is disposed over the second barrier layer and creates a contact.

A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

An anisotropic conductive film (ACF) is formed with an ordered array of discrete regions that include a conductive carbon-based material. The discrete regions, which may be formed at small pitch, are embedded in at least one adhesive dielectric material. The ACF may be used to mechanically and electrically interconnect conductive elements of initially-separate semiconductor dice in semiconductor device assemblies. Methods of forming the ACF include forming a precursor structure with the conductive carbon-based material and then joining the precursor structure to a separately-formed structure that includes adhesive dielectric material to be included in the ACF. Sacrificial materials of the precursor structure may be removed and additional adhesive dielectric material formed to embed the discrete regions with the conductive carbon-based material in the adhesive dielectric material of the ACF.

A chip structure, a wafer structure and a method for manufacturing the same are provided in the present disclosure. A first chip and a second chip are bonded by bonding layers of a dielectric material. Top wiring layers are led out through bonding via holes from a back surface of a bonded chip. The bonding via holes are used for bonding and are surrounded by the bonding layers. A top wiring layer of a third chip is led out through bonding pads formed in a bonding layer. The bonding via holes are aligned with and bonded to the bonding pads to achieve bonding of the three chips. The top wiring layer of the third chip is led out from the back surface of the third chip through a lead-out pad.