A manufacturing method of a semiconductor apparatus includes preparing an intermediate member that includes a first member having a first substrate comprising a semiconductor element formed thereon, a second member having a second substrate, the second substrate including a part of a circuit electrically connected to the semiconductor element and having a linear expansion coefficient different from that of the first substrate, and a third member having a third substrate showing such a linear expansion coefficient that a difference between itself and the linear expansion coefficient of the first substrate is smaller than a difference between the linear expansion coefficients of the first substrate and the second substrate, and includes bonding the first member and the second member together. A first bonding electrode containing copper electrically connected to the semiconductor element and a second bonding electrode containing copper electrically connected to the circuit are bonded together.

A semiconductor package includes a first chip, an insulating protection layer, a second chip, a plurality of second conductive bumps and an underfill. The insulating protection layer is disposed on a first active surface of the first chip and includes a concave. Projections of a plurality of first inner pads and a plurality of first outer pads of the first chip projected on the insulating protection layer are located in the concave and out of the concave, respectively. The second chip is flipped on the concave and includes a plurality of second pads. Each of the first inner pads is electrically connected to the corresponding second pad through the corresponding second conductive bump. The underfill is disposed between the concave and the second chip and covers the second conductive bumps.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure including a first substrate, and a first circuit layer positioned on the first substrate, a first redistribution structure positioned on the first circuit layer, and a second semiconductor structure including a second circuit layer positioned on the first redistribution structure, and a second substrate positioned on the second circuit layer. A layout of the first circuit layer and a layout of the second circuit layer are substantially the same and the first redistribution structure is electrically coupled to the first semiconductor structure and the second semiconductor structure.

A semiconductor device includes a first semiconductor die having a top planar surface and a second semiconductor die having a bottom planar surface and a top planar surface. A protective layer including a bottom planar surface and a top planar surface is positioned between the first semiconductor die and the second semiconductor die. An adhesive layer having a top planar surface and a bottom planar surface is between the protective layer and the second semiconductor die. A periphery of the top planar surface of the first semiconductor die is covered by a periphery of the bottom planar surface of the protective layer after cutting a portion of the protective layer that extended past the periphery of the surface of the first semiconductor die. The protective layer reduces the occurrence of peeling of the second semiconductor die and first semiconductor die coupled to the protective layer.

Disclosed are an array substrate, and a display device, and a method for manufacturing the same. The array substrate includes: a base substrate, and a thin film transistor, a planarization pattern, a bonding pattern, and a conductive structure that are disposed on the base substrate. The thin film transistor, the planarization pattern, and the bonding pattern are laminated in a direction going distally from the base substrate. The planarization pattern is provided with a via and a groove, the conductive structure is disposed in the via, wherein the bonding pattern is conductive and is electrically connected to the thin film transistor by the conductive structure, an orthographic projection of the bonding pattern on the base substrate falls outside an orthographic projection of the groove on the base substrate, and the groove is configured to accommodate an adhesive.

Methods of forming a back side image sensor device, as well as back side image sensor devices formed, are disclosed. In one such a method, an image sensor wafer having a first dielectric layer with a first surface is obtained. A reconstituted wafer having a processor die and a second dielectric layer with a second surface is obtained. The reconstituted wafer and the image sensor wafer are bonded to one another including coupling the first surface of the first dielectric layer and the second surface of the second dielectric layer. In another method, such formation is for a processor die bonded to an image sensor wafer. In yet another method, such formation is for a processor die bonded to an image sensor die.

Embodiments of bonded 3D memory devices and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a first semiconductor structure, which includes a plurality of first NAND memory strings, a plurality of first BLs, at least one of the first BLs being conductively connected to a respective one of the first NAND memory strings; and a first bonding layer having a plurality of first bit line bonding contacts conductively connected to the plurality of first BLs, respectively. The 3D memory device further includes a second semiconductor structure, which includes a plurality of second NAND memory strings, a plurality of second BLs, at least one of the second BLs being conductively connected to a respective one of the second NAND memory strings, and a second bonding layer having a plurality of second bit line bonding contacts conductively connected to the plurality of second BLs, respectively.

A hybrid bonding structure and a semiconductor including the hybrid bonding structure are provided. The hybrid bonding structure includes a solder ball and a solder paste bonded to the solder ball. The solder paste may include solder particles including at least one of In, Zn, SnBiAg alloy, or SnBi alloy, and ceramic particles. The solder paste may include a flux. The solder particles may include Sn(42.0 wt %)-Ag(0.4 wt %)-Bi(57.5−X) wt %, and the ceramic particles include CeO.sub.2(X) wt %, where 0.05≤X≤0.1.

In some embodiments, a display module for implementing an image using an inorganic light emitting device includes a substrate, a thin film transistor (TFT) layer provided on the substrate, a plurality of connection pads provided on the TFT layer, an anisotropic conductive layer provided on the TFT layer, an inorganic light emitting element bonded to the anisotropic conductive layer, and a conductive ball control layer provided in a surrounding area of the plurality of connection pads. The anisotropic conductive layer includes an adhesive layer and a plurality of conductive balls distributed inside the adhesive layer. The inorganic light emitting element includes a plurality of electrodes corresponding to the plurality of connection pads. The conductive ball control layer is configured to restrict the plurality of conductive balls from moving in a direction perpendicular to a bonding direction while the inorganic light emitting element is being bonded to the anisotropic conductive layer.

A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.