Patent classifications
H01L2224/40175
CHIP PACKAGE MODULE, METHOD FOR MANUFACTURING SAME, POWER MODULE, AND ELECTRONIC DEVICE
A chip package module, including a first conductive frame, a first bare die disposed on the first conductive frame, and a second conductive frame disposed at an interval beside the first conductive frame. The chip package module further includes a first conductive connecting sheet, a second bare die, and a conductive cover plate. The first conductive connecting sheet is connected to a surface of the first bare die away from the first conductive frame, and extends to be lapped on the second conductive frame. The second bare die is laminated on the first bare die and is connected to the first conductive connecting sheet. The conductive cover plate is connected to a surface of the second bare die away from the first conductive frame and extends to be connected to the first conductive frame.
Plurality of transistors attached to a heat sink with a periphery notch
This semiconductor device includes: a heat dissipation plate formed in a plate shape; a plurality of switching elements joined to one surface of the heat dissipation plate; a first terminal extending in a direction away from the heat dissipation plate in a state of being apart from the heat dissipation plate, the first terminal being connected via a first electric conductor to surfaces of the plurality of switching elements on an opposite side to the heat dissipation plate side; and a sealing member sealing the plurality of switching elements, the heat dissipation plate, and the first terminal. A notch is provided in an outer periphery portion of the heat dissipation plate. A portion of the first terminal on the heat dissipation plate side overlaps with a region of a cut at the notch as seen in a direction perpendicular to the one surface of the heat dissipation plate.
CLIP AND RELATED METHODS
Implementations of a clip for a semiconductor package may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.
STRUCTURE TO REDUCE CHIP SHIFT DURING ASSEMBLY
A semiconductor device, apparatus, structure, and associated methods thereof. The device includes a semiconductor chip, a ring structure configured to retain a lattice having a plurality of cells, the ring structure and the lattice being coupled to the semiconductor chip, one or more semiconductor device connection components being coupled to the semiconductor chip using one or more binding components disposed within the ring structure and the lattice, and a housing configured to encapsulate the semiconductor chip, the ring structure and the lattice, and the one or more semiconductor device connection components.
Package with Single Integral Body Carrying Two Transistor Chips with Half Bridge Configuration
A package includes a single integral electrically conductive body, a first chip with an integrated transistor and including a first terminal, a second terminal, and a third terminal, wherein the second terminal and the third terminal are formed on one main surface of the first chip and the first terminal is formed on an opposing main surface of the first chip, and a second chip with an integrated transistor and comprising a fourth, fifth and sixth terminals, wherein the fourth terminal and the sixth terminal are formed on one main surface of the second chip and the fifth terminal is formed on another surface of the second chip, wherein the first chip and the second chip are connected to form a half bridge.
SEMICONDUCTOR DEVICE
A cooling case has outer lateral surfaces located on long sides and outer lateral surfaces located on short sides thereof in plan view. The cooling case has a flow passage having a concave shape therein. The flow passage includes a main passage, and an inflow passage recessed from a bottom surface of the main passage toward a bottom side of the cooling case. The cooling case further has an inlet that is provided at one of the outer lateral surface to be directly connected to the inflow passage. The inlet introduces a cooling medium that flows through the inlet in a longitudinal direction of the cooling case toward the flow passage and the inflow passage has a diffusion surface that faces an opening of the inlet.
Semiconductor package having mold locking feature
A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles comprising a first die paddle. The first die paddle comprises one or more through holes, one or more protrusions with grooves on top surfaces of the one or more protrusions, or one or more squeezed extensions. Each of the one or more through holes is filled with a respective portion of the molding encapsulation. Each of the one or more through holes may be of a rectangular shape, a rectangular shape with four filleted corners, a circular shape, or an oval shape. Each of the grooves is filled with a respective portion of the molding encapsulation. A respective side wall of each of the one or more squeezed extensions is of a swallowtail shape. The swallowtail shape directly contacts the molding encapsulation.
Clip and related methods
A clip for a semiconductor package. Implementations may include: an electrically conductive clip having a first end and a second end and a middle section between the first end and the second end. The first end may be configured to couple to a first die through a bonding material. The second end may be configured to couple to a second die through a bonding material. The middle section may be configured to couple to an emitter structure through a bonding material. The clip may include an integrally formed electrically conductive material and include an M-shape. A middle of the M-shape may be coupled to the emitter structure.
SEMICONDUCTOR MODULE AND MANUFACTURING METHOD THEREOF
A semiconductor module manufacturing method includes: preparing an insulating wiring substrate 10 including a substrate and a first conductor provided on the substrate, a semiconductor chip 20 having a first surface and a second surface, and a printed wiring board 50 including an insulating substrate and a lead frame 52 provided on the insulating substrate, the lead frame including a first portion 52a provided in a first via-hole penetrating through the insulating substrate; disposing the first surface on the first conductor via a first sintering material; disposing an insulating sheet on the insulating wiring substrate to surround the semiconductor chip; disposing the printed wiring board such that the insulating substrate faces the insulating sheet and the first portion makes contact with the second surface via a second sintering material; and heating the insulating wiring substrate, the semiconductor chip, the insulating sheet, and the printed wiring board while they are pressurized.
SEMICONDUCTOR MODULE
A semiconductor module includes a conductive substrate, a plurality of first semiconductor elements, and a plurality of second semiconductor elements. The conductive substrate includes a first conductive portion to which the plurality of first semiconductor elements are electrically bonded, and a second conductive portion to which the plurality of second semiconductor elements are electrically bonded. The semiconductor module further includes a first input terminal, a second input terminal, and a third input terminal that are provided near the first conductive portion. The second input terminal and the third input terminal are spaced apart from each other with the first input terminal therebetween. The first input terminal is electrically connected to the first conductive portion. A polarity of the first input terminal is set to be opposite to a polarity of each of the second input terminal and the third input terminal.