H01L2224/48138

BOND PAD STRUCTURE WITH REDUCED STEP HEIGHT AND INCREASED ELECTRICAL ISOLATION
20220115345 · 2022-04-14 ·

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a first bond pad isolation structure within a substrate. A second bond pad isolation structure is formed with the substrate. The second bond pad isolation structure is disposed laterally between inner sidewalls of the first bond pad isolation structure. The first bond pad isolation structure and the second bond pad isolation structure are formed concurrently with one another. A bond pad is formed extending through the substrate. The bond pad comprises a conductive body overlying the second bond pad isolation structure and a conductive protrusion extending from the conductive body to below the substrate. The second bond pad isolation structure laterally wraps around the conductive protrusion.

METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.

SEMICONDUCTOR PACKAGE
20210327844 · 2021-10-21 ·

A semiconductor package includes a first chip and a second chip arranged side by side on a carrier substrate. The first chip is provided with a high-speed signal pads along a first side in proximity to the second chip. The second chip includes a redistribution layer, and the redistribution layer is provided with data (DQ) pads along the second side in proximity to the first chip. A plurality of first bonding wires is provided to directly connect the high-speed signal pads to the DQ pads. The redistribution layer of the second chip is provided with first command/address (CA) pads along the third side opposite to the second side, and a plurality of dummy pads corresponding to the first CA pads. The plurality of dummy pads are connected to second CA pads disposed along a fourth side of the second chip via interconnects of the redistribution layer.

Semiconductor device packages with high angle wire bonding and non-gold bond wires

In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

BOND PAD STRUCTURE WITH REDUCED STEP HEIGHT AND INCREASED ELECTRICAL ISOLATION
20210066225 · 2021-03-04 ·

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond pad disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. An upper surface of the semiconductor substrate is vertically below the back-side surface. The bond pad extends through the semiconductor substrate. The bond pad includes a conductive body over the upper surface of the semiconductor substrate and conductive protrusions extending from above the upper surface to below the front-side surface of the semiconductor substrate. A vertical distance between a top surface of the bond pad and the back-side surface of the semiconductor substrate is less than a height of the conductive protrusions. A first bond pad isolation structure extends through the semiconductor substrate and laterally surrounds the conductive protrusions.

RADIOFREQUENCY TRANSMISSION/RECEPTION DEVICE
20200381829 · 2020-12-03 ·

A radiofrequency transmission/reception device includes a first and a second conductive wire element, a first far-field transmission/reception chip and a second near-field transmission/reception chip. The first and the second wire element combine with the characteristic impedance of the second transmission/reception chip in order to form a coupling device associated with the first transmission/reception chip at the operating frequency of the first chip. The first and the second wire element combine with the characteristic impedance of the first transmission/reception chip in order to form a coupling device associated with the second transmission/reception chip at the operating frequency of the second chip.

Method of making a wire support leadframe for a semiconductor device

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

Bonding wire having a silver alloy core, wire bonding method using the bonding wire, and electrical connection part of semiconductor device using the bonding wire

A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

Wire support for a leadframe

A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.

METHOD FOR INSERTING A WIRE INTO A GROOVE OF A SEMICONDUCTOR CHIP, AND PIECE OF EQUIPMENT FOR IMPLEMENTING SUCH A METHOD

A method for inserting a wire into a longitudinal groove of a semiconductor chip for the assembly thereof, the groove containing a pad made of a bonding material having a set melting point, the method comprises: in a positioning step, placing a longitudinal section of the wire along the groove, in forced abutment against the pad; and, in an insertion step, exposing a zone containing at least one portion of the pad to a processing temperature higher than the melting point of the bonding material and for a sufficient time to make the pad at least partially melt, and causing the wire to be inserted into the groove. The present disclosure also relates to a piece of equipment allowing the insertion method to be implemented.