An electronic circuit includes a circuit carrier (1), a metal layer (9) and an electrically insulating base layer (2) on the metal layer (9). Conductor tracks (3) are on the base layer (2) and electronic components (4) are arranged on the conductor tracks (3). The conductor tracks (3) and the electronic components (4) are covered using a potting compound (10). A separating layer (11) is arranged between the base layer (2) and the potting compound (10) at least in the areas between the conductor tracks (3). The separating layer (11) consists of an electrically insulating material, which is different from both the material of the base layer (2) and the material of the potting compound (10).

An electronic device includes a molded package structure and a conductive lead partially exposed outside the package structure, the package structure having lateral sides extending at an angle that is greater than 15 degrees and 25 degrees or less to facilitate mold cavity filling during package molding and mitigate mold voids in the electronic device. A method of fabricating an electronic device includes attaching a die to a lead frame, electrically coupling a conductive terminal of the die to a conductive lead and performing a molding process using a mold having cavity sidewalls with a draft angle greater than 15 degrees and 25 degrees or less to form a package structure that encloses the die and partially encloses the conductive lead.

A semiconductor device includes a semiconductor element and a conductive bond bonding the semiconductor element to a support. The semiconductor element has first to fourth sides, and the bond has first to fourth edges. Distance between the first side and the first edge in first direction is greater at ends than at the center of the first side in second direction crossing first direction. Distance between the second side and the second edge in first direction is greater at ends than at the center of the second side in second direction. Distance between the third side and the third edge in second direction is greater at ends than at the center of the third side in first direction. Distance between the fourth side and the fourth edge in second direction is greater at ends than at the center of the fourth side in first direction.

A semiconductor package includes a molding compound, a chip and a conductive pad, wherein the chip is electrically connected to the conductive pad and both are encapsulated in the molding compound. An anchor flange is formed around a top surface of the conductive pad by over plating. When the conductive pad is embedded in the molding compound, the anchor flange engages the molding compound to prevent the conductive pad from separation. Bottoms of a chip and the conductive pad are exposed from the molding compound for electrically soldering to a circuit board.

A semiconductor device includes first and second semiconductor elements, a conductive support, a third semiconductor element and a sealing resin. The conductive support includes first and second leads spaced apart in a first direction. The first semiconductor element is supported by the first lead. The second semiconductor element is supported by the second lead. The third semiconductor element, supported by the conductive support, insulates the first semiconductor element and the second semiconductor element. The sealing resin covers a part of the conductive support. A distance d1 between the first lead and the second lead in the first direction is greater than distance d0 given by Equation below. In Equation below, Y is the number of years of insulation life (years) expected for the semiconductor device, A and B are constants determined by a material of the sealing resin, and X is a voltage (kVrms).

[00001]$d0=\sqrt[B]{\frac{Y}{A}}\times 0.15\times X$

A semiconductor device includes at least one member that is partially sealed by a sealing material and has a part of thereof being exposed from the sealing material, a reversible temperature indicating material, and an irreversible temperature indicating material. Each of the reversible temperature indicating material and the irreversible temperature indicating material is provided on a surface of any one of the at least one member.

In a described example, an apparatus includes: a package substrate having a die pad configured for mounting a semiconductor die, and leads spaced from the die pad; a semiconductor die mounted on the die pad; a fuse mounted to a lead, the fuse having a fuse element coupled between a fuse cap and the lead, the fuse having a fuse body with an opening surrounding the fuse element, the fuse cap attached to the fuse body; electrical connections coupling the semiconductor die to the fuse; and mold compound covering the semiconductor die, the fuse, the electrical connections, and a portion of the package substrate, with portions of the leads exposed from the mold compound to form terminals.

An electric drive unit having a stator, a rotor received in the stator and rotatable about a central longitudinal axis, and an inverter assembly that includes a plurality of power semiconductors, a plurality of heat sinks and an end plate. The power semiconductors are thermally coupled to the heat sinks. Each of the heat sinks has a plurality of fins that extend into a flow channel that is coaxial with the plurality of sets of field windings. The end plate is coupled to the power semiconductors and has a projection, which is sealingly coupled to the stator and which and partly defines an annular cavity, and a coolant port that is coupled in fluid communication with the annular cavity. The flow channel is in fluid communication with and disposed in a flow path between the annular cavity and the cooling channels in the stator body.

There is provided a power semiconductor module with multiple semiconductor chips arranged in parallel on an insulated substrate, allowing for high density mounting of semiconductor chips and highly reliable with less difference in operating characteristics from one semiconductor chip to another. The above module includes an insulated substrate; a first conductive pattern laid out on the insulated substrate; multiple power semiconductor chips arranged on the first conductive pattern; a first wiring formed to bridge and directly connecting respective gate electrodes of the power semiconductor chips; and a second wiring formed to bridge and directly connecting respective source electrodes of the power semiconductor chips, wherein the first wiring is placed alongside of the second wiring and may be angled within 30 degrees with respect to the second wiring.

A europium-doped β-sialon phosphor, in which, when the ratio of an aluminum element at a depth of 8 nm from the surface of the phosphor, which is obtained by X-ray photoelectron spectroscopy, is indicated by P.sub.8 [at %], and the ratio of an aluminum element at a depth of 80 nm from the surface of the phosphor is indicated by P.sub.80 [at %], P.sub.8/P.sub.80≤0.9 is satisfied. A light emitting device containing this β-sialon phosphor.