A packaged RF transistor amplifier includes an RF transistor amplifier die having a first terminal, a first lead, an integrated passive device that includes a first series microstrip transmission line, a first bond wire coupled between the first terminal and the first series microstrip transmission line, and a second bond wire coupled between the first series microstrip transmission line and the first lead.

An integrated circuit (IC) includes semiconductor substrate with a metal stack including a lower, upper and a top metal layer that includes bond pads and a detection bond pad (DBP). A wirebond damage detector (WDD) includes the DBP over a first and second connected structure. The first and second connected structures both include spaced apart top segments of the upper metal layer coupled to spaced apart bottom segments of the lower metal layer. The DBP is coupled to one end of the first connected structure, and ≥1 metal trace is coupled to another end extending beyond the DBP to a first test pad. The second connected structure includes metal traces coupled to respective ends each extending beyond the DBP to a second test pad and to a third test pad.

A switching device includes: a switching element; a die pad; a gate terminal; a first power terminal integral with the die pad; and a second power terminal, the gate terminal, the first power terminal, and the second power terminal are located on a side of a first direction of the die pad, the gate terminal, the first power terminal, and the second power terminal are arranged in a second direction orthogonal to the first direction in the following order: the gate terminal, the first power terminal, and the second power terminal or the second power terminal, the first power terminal, and the gate terminal, the switching element includes a first and a second gate pad, the first gate pad is closer to the gate terminal than the second gate pad is, the second gate pad is closer to the second power terminal than the first gate pad is.

A power die package includes a lead frame having a flag with power leads on one lateral side and signal leads on one or more other lateral sides. A power die is attached to a bottom surface of the flag and electrically connected to the power leads with a conductive epoxy. A control die is attached to a top surface of the flag and electrically connected to the signal leads with bond wires. A mold compound is provided that encapsulates the dies, the bond wires, and proximal parts of the leads, while distal ends of the leads are exposed, forming a PQFN package.

In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

An electronic device includes an integrated circuit package including a die mounted on a die carrier, a mold structure at least partially encapsulating the mounted die, and a heat transfer chimney formed on the die. The heat transfer chimney extends at least partially through the mold structure to transfer heat away from the die. The heat transfer chimney is formed from a thermally conductive compound including thermally conductive nanoparticles.

A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

A semiconductor device includes a semiconductor element, first and second leads, and a sealing resin. The semiconductor element includes first and second electrodes. The first lead includes a mounting base having a main face to which the first electrode is bonded and a back face, and includes a first terminal connected to the first electrode. The second lead includes a second terminal connected to the second electrode. The sealing resin includes a main face and a back face opposite to each other, and includes an end face oriented in the protruding direction of the terminals. The back face of the mounting base is exposed from the back face of the resin. The sealing resin includes a groove formed in its back face and disposed between the back face of the mounting base and a boundary between the second terminal and the end face of the resin.

A packaged power semiconductor device includes a power semiconductor wafer, a heat conduction layer, and a heat sink that are sequentially stacked, and a sealing part configured to wrap and seal the power semiconductor wafer and at least part of the heat conduction layer. The packaged power semiconductor device further includes a pin, where the pin includes a connection segment wrapped inside the sealing part, and an extension segment located outside the sealing part. The connection segment is electrically connected to the power semiconductor wafer, and a shortest distance between the extension segment and a first outer surface is greater than a creepage distance corresponding to a highest working voltage of the power semiconductor wafer. This can avoid a creepage phenomenon of the pin by limiting a distance between the first outer surface and the extension segment that is of the pin and that is exposed outside the sealing part.

An electrical assembly that with an inverter that is mounted to the field windings of a stator. The inverter has a plurality of power semiconductor packages (PSP), each of which including a semiconductor die, a plurality of electric terminals, which are electrically coupled to the semiconductor die, and a heat sink with a base, which is fixedly and electrically coupled to one of the electric terminals, and a plurality of fins that extend axially from the base in a direction away from the semiconductor die. The PSP's are arranged in a circumferentially spaced apart manner. The fins are arranged in rows and are progressively longer in length from a radially-inner most fin to a radially-outer most fin. Slots are formed in the base on a radially-inner side of the base. Each slot extends toward a radially-outer side of the base and intersects a corresponding one of the rows of fins.