The present invention discloses a bonding-wire-type heat sink structure for semiconductor devices. An embodiment of the said bonding-wire-type heat sink structure comprises: a semiconductor substrate; a heat source formed on or included in the semiconductor substrate, said heat source including at least one hot spot; at least one heat conduction layer; at least one heat conductor connecting the at least one hot spot with the at least one heat conduction layer; at least one heat dissipation component in an electrically floating state; and at least one bonding wire connecting the at least one heat conduction layer with the at least one heat dissipation component, so as to transmit the heat of the heat source to the heat dissipation component.

A semiconductor module comprises a semiconductor device; a substrate, on which the semiconductor device is attached; a molded encasing, into which the semiconductor device and the substrate are molded; at least one power terminal partially molded into the encasing and protruding from the encasing, which power terminal is electrically connected with the semiconductor device; and an encased circuit board at least partially molded into the encasing and protruding over the substrate in an extension direction of the substrate, wherein the encased circuit board comprises at least one receptacle for a pin, the receptacle being electrically connected via the encased circuit board with a control input of the semiconductor device.

A semiconductor module includes an insulating substrate having a main wiring layer, positive and negative electrode terminals adjacently arranged in a first direction, a plurality of semiconductor elements forming a first column and another plurality of semiconductor elements forming a second column, each semiconductor element having gate and source electrode on an upper surface thereof, and being disposed on the main wiring layer such that corresponding ones of the gate electrodes in the first and second columns face each other in a second direction orthogonal to the first direction, a control wiring substrate between the first and second columns and having gate and source wiring layers, a gate wiring member connecting ones of the gate electrodes in the first and second columns through the gate wiring layer, and a source wiring member connecting ones of the source electrodes in the first and second columns through the source wiring layer.

RF transistor amplifiers include an RF transistor amplifier die having a Group III nitride-based semiconductor layer structure and a plurality of gate terminals, a plurality of drain terminals, and at least one source terminal that are each on an upper surface of the semiconductor layer structure, an interconnect structure on an upper surface of the RF transistor amplifier die, and a coupling element between the RF transistor amplifier die and the interconnect structure that electrically connects the gate terminals, the drain terminals and the source terminal to the interconnect structure.

A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.

Reduction in impedance in a lead connected to a semiconductor element is achieved while achieving anchor effect. The semiconductor device includes a heatsink, a semiconductor element, a lead disposed on an upper side of the heatsink, and a molding material formed to cover the lead, the heatsink, and the semiconductor element. Formed on an edge portion of a lower surface in a position, in the heatsink, overlapping with the lead in a plan view is a first convex portion protruding more than an edge portion of an upper surface in the position, and formed on an edge portion of an upper surface in a position, in the heatsink, which does not overlap with the lead in a plan view is a second convex portion protruding more than an edge portion of a lower surface in the position.

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

A deteriorated section identifying unit refers to correspondence information that defines a deteriorated section of a plurality of bonding sections to the emitter electrode surface to which the first bonding wires are connected, for a combination of temporal change of a first voltage that is a difference between a potential at a collector main terminal and a potential at the emitter main terminal and temporal change of a second voltage that is a difference between a potential at the emitter reference terminal and a potential at the emitter main terminal, and identifies the deteriorated section corresponding to a combination of temporal change of the first voltage measured by a first voltage measuring circuit and temporal change of the second voltage measured by a second voltage measuring circuit.

A light emitting device package includes a first molding member surrounding a heat dissipation frame, a first electrode frame, and a second electrode frame; a first semiconductor light emitting device on the heat dissipation frame and having first and second pads; a second semiconductor light emitting device on the heat dissipation frame and having first and second pads; a wavelength conversion layer on the first and second semiconductor light emitting structures; a first bonding wire connected to the first pad of the first semiconductor light emitting device and the first electrode frame; a second bonding wire connected to the second pad of the second semiconductor light emitting device and the second electrode frame; and an inter-chip bonding wire connecting the second pad of the first semiconductor light emitting device to the first pad of the second semiconductor light emitting device.

A semiconductor device has a leadframe and a first electrical component including a first surface disposed on the leadframe. A first clip bond is disposed over a second surface of the first electrical component. The first clip bond extends vertically through the semiconductor device. The first clip bond has a vertical member, horizontal member connected to the vertical member, die contact integrated with the horizontal member, and clip foot extending from the vertical member. A second electrical component has a first surface disposed on the first clip bond. A second clip bond is disposed over a second surface of the second electrical component opposite the first surface of the second electrical component. An encapsulant is deposited around the first electrical component and first clip bond. A second electrical component is disposed over the encapsulant. The clip foot is exposed from the encapsulant.