An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A transistor package having four terminals includes a semiconductor transistor chip and a semiconductor diode chip. The semiconductor transistor chip includes a control electrode and a first load electrode on a first surface and a second load electrode on a second surface opposite the first surface. The semiconductor diode chip includes a first diode electrode on a first surface and a second diode electrode on a second surface opposite the first surface. The transistor package includes a first terminal electrically connected to the control electrode, a second terminal electrically connected to the first diode electrode, a third terminal electrically connected to the first load electrode and a fourth terminal electrically connected to the second load electrode. At least the first terminal, the second terminal and the third terminal protrude from one side of transistor package. The first terminal is arranged between the second terminal and the third terminal.

A lead frame includes a die pad and electrical leads. An integrated circuit chip is mounted to the die pad. An encapsulating package has a perimeter defined by first, second, third and fourth sidewalls. The electrical leads extend from the opposed first and second sidewalls of the package. At least one sidewall of the opposed third and fourth sidewalls of the package includes a V-shaped concavity functioning to increase a creepage distance between the electrical leads at the opposed first and second sidewalls.

A semiconductor device includes a die pad, a semiconductor element, a joining layer, a first conductive member, and a second conductive member. The semiconductor element has a first electrode opposing an obverse surface of the die pad, and a second electrode and a third electrode that are opposite to the first electrode in a thickness direction. The first electrode is electrically joined to the obverse surface. The joining layer electrically joins the first electrode and the obverse surface to each other. The first conductive member is electrically joined to the second electrode. The second conductive member is electrically joined to the third electrode. The area of the third electrode is smaller than the area of the second electrode as viewed along the thickness direction. The Young's modulus of the second conductive member is smaller than the Young's modulus of the first conductive member.

A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

A light-emitting element package according to an embodiment comprises: a body comprising a cavity; the cavity; a first frame and a second frame arranged on the bottom surface of the cavity; a first metal layer disposed on the first frame; an ultraviolet light-emitting element disposed on the first metal layer; and a second metal layer disposed on the second frame and electrically connected to the second frame, wherein the body comprises a separation portion between the first frame and the second frame, the second metal layer extends over the sloping surface of the cavity and the separation portion of the body, and the second metal layer is spaced apart from the first metal layer in the cavity and surrounds the first metal layer.

A semiconductor device capable of securing an insulation distance between a semiconductor element and a wiring. The semiconductor device includes a first semiconductor element, a second semiconductor element, a first wiring, and a second wiring. The first semiconductor element includes a first main surface and a second main surface. An electrode is formed on the first main surface. The second semiconductor element is disposed at a position different from a position of the first semiconductor element in a thickness direction. The first wiring includes an end connected to the electrode. The end includes an upper surface and a cut surface. Diameter of the second wiring is smaller than diameter of the first wiring. The second wiring includes a first end and a second end. The first end is directly connected to the upper surface of the end of the first wiring.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).

In some examples, a semiconductor package comprises a semiconductor die having a first surface and a second surface opposing the first surface. The package comprises an orifice extending through a thickness of the semiconductor die from the first surface to the second surface. The package comprises a set of metallic nanowires positioned within the orifice and extending through the thickness of the semiconductor die from the first surface to the second surface.

A semiconductor package includes a first die pad, a first semiconductor die mounted on the first die pad, an encapsulant body of electrically insulating material that encapsulates first die pad and the first semiconductor die, a plurality of package leads that each protrude out of a first outer face of the encapsulant body, a connection lug that protrudes out of a second outer face of the encapsulant body, the second outer face being opposite from the first outer face. The first semiconductor die includes first and second voltage blocking terminals. The connection lug is electrically connected to one of the first and second voltage blocking terminals of the first semiconductor die. A first one of the package leads is electrically connected to an opposite one of the first and second voltage blocking terminals of the first semiconductor die that the first connection lug is electrically connected to.