Patent classifications
H01L2224/48245
Pre-molded lead frames for semiconductor packages
One example of a pre-molded lead frame includes a mold body, a plurality of recesses, and a plurality of first leads. The mold body includes a first main surface and a second main surface opposite to the first main surface. Each recess of the plurality of recesses extends from the first main surface into the mold body. The plurality of first leads are coupled to the mold body and extend from a third surface of the mold body. The third surface extends between the first main surface and the second main surface.
SEMICONDUCTOR DEVICE
A semiconductor device includes: a rectangular RC-IGBT; an IC chip electrically connected to the RC-IGBT; a plurality of control terminals electrically connected to the IC chip; a plurality of power terminals electrically connected to the RC-IGBT; and a rectangular sealing resin covering the RC-IGBT and the IC chip. The RC-IGBT has an aspect ratio of 1.62 or more, the sealing resin has a lengthwise length of 44 mm or smaller, and the semiconductor device has a rated current of 25 A or more.
SEMICONDUCTOR DEVICE
A semiconductor device includes: an insulating substrate; a semiconductor chip; a base plate; a first heat dissipating material; and a case. The semiconductor chip and a sealing material for sealing the semiconductor chip are housed in the case. The insulating substrate includes an insulating layer and a conductor pattern provided on an upper surface of the insulating layer. The semiconductor chip is joined onto the conductor pattern by a joining material. A lower surface of the insulating substrate and an upper surface of the base plate are in contact with each other with interposition of the first heat dissipating material. The insulating substrate and the base plate are not fixed to each other.
SEMICONDUCTOR DEVICE PACKAGES WITH HIGH ANGLE WIRE BONDING AND NON-GOLD BOND WIRES
In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.
ELECTRONIC DEVICE PACKAGING WITH GALVANIC ISOLATION
In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including a first leadframe portion including a first plurality of signal leads, and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include one or more semiconductor die that are electrically coupled with the substrate and the leadframe portions.
Semiconductor Package with Releasable Isolation Layer Protection
A semiconductor device includes a semiconductor package, including a package body that includes an encapsulant portion and an isolation structure, a semiconductor die embedded within the package body, and a plurality of leads that protrude out from the encapsulant body, wherein the encapsulant portion and the isolation structure are each electrically insulating structures, wherein the isolation structure has a greater thermal conductivity than the encapsulant portion, and wherein the isolation structure is thermally coupled to the semiconductor die, and a releasable layer affixed to the semiconductor package, wherein a first outer face of the package body includes a first surface of the isolation structure, wherein the releasable layer at least partially covers the first surface of the isolation structure, and wherein the releasable layer is releasable from the semiconductor package.
Integrated circuit package with partitioning based on environmental sensitivity
An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.
Power Semiconductor Module with Laser-Welded Leadframe
A power semiconductor module includes a substrate with a structured metallization layer and a number of semiconductor chips. Each chip has a first power electrode bonded to the metallization layer. A leadframe is laser-welded to second power electrodes of the semiconductor chips for electrically interconnecting the semiconductor chips. A control conductor is attached to the leadframe opposite to the semiconductor chips and is electrically isolated from the leadframe. The control conductor is electrically connected to control electrodes of the semiconductor chips in the group.
INTELLIGENT POWER MODULE
An intelligent power module includes: an encapsulating material structure; a lead frame which is at least partially encapsulated inside the encapsulating material structure, wherein all portions of the lead frame encapsulated inside the encapsulating material structure are at a same planar level; and a heat dissipation structure, which is connected to the lead frame.
Semiconductor light emitting device
Semiconductor light emitting device includes: substrate including main and back surfaces, first and second side surfaces, and bottom and top surfaces, wherein main surface includes first to fourth sides; first main surface electrode on main surface and including first base portion contacting the sides of the main surface, and die pad connected to first base portion; second main surface electrode disposed on the main surface and including second base portion contacting first and third sides of the main surface, and wire pad connected to second base portion; semiconductor light emitting element including first electrode pad and mounted on die pad; wire connecting first electrode pad and wire pad; first insulating film covering portion between first base portion and die pad; second insulating film covering portion between second base portion and wire pad and having end portions contacting main surface; and light-transmitting sealing resin.