Shielding for flip chip devices. In some embodiments, a shielded assembly can include a substrate and a flip chip die having a front side and a back side, with the including an integrated circuit implemented on the front side, and the front side of the flip chip die being mounted to the substrate. The shielded assembly can further include a shielding component implemented over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

Shielding for flip chip devices. In some embodiments, a shielded assembly can include a substrate and a flip chip die having a front side and a back side, with the including an integrated circuit implemented on the front side, and the front side of the flip chip die being mounted to the substrate. The shielded assembly can further include a shielding component implemented over the back side of the flip chip die to provide electromagnetic shielding between a first region within or on the flip chip die and a second region away from the flip chip die.

A semiconductor light emitting device includes a light emitting module, a stem, and a surrounding member. The stem includes a conductive base and a conductive heat sink extending upright from the base. The light emitting module is mounted on the heat sink. The surrounding member is arranged on the base and surrounds the light emitting module and the heat sink. The light emitting module includes a substrate mounted on the heat sink, a light emitting element mounted on the substrate, and a light emitting element drive circuit mounted on the substrate. The light emitting element drive circuit includes a transistor configured to drive the light emitting element. The transistor is a vertical MOSFET mounted on the substrate.

A wire bonding apparatus connecting a lead of a mounted member with an electrode of a semiconductor die through a wire comprises a capillary through which the wire is inserted, a shape acquisition part which acquires the shape of the lead to which the wire is connected, a calculating part which calculates an extending direction of a wire tail extending from the end of the capillary based on the shape of a lead to which the wire is connected next, and a cutting part which moves the capillary in the extending direction and cuts the wire to form the wire tail after the lead is connected with the electrode through the wire. Thus, in the wire bonding using wedge bonding, joining part tails (183a, 283a, 383a) formed in continuation to a first bonding point can be prevented from coming into contact with each other.

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

A semiconductor package includes a substrate having a top planar surface and a semiconductor die mounted on the top planar surface of the substrate. Bond wires electrically connect the semiconductor die to the substrate. Flow control dams are integrally formed with the top planar surface of the substrate and each flow control dam protrudes from the top planar surface of the substrate at a location proximate to the bond wires. The flow control dams reduce the occurrence of wire sweep in the bond wires electrically connected to the substrate and semiconductor die.

Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

A semiconductor device has an interposer and a surface mount technology (SMT) component disposed on the interposer. The interposer is disposed on an active surface of a semiconductor die. The semiconductor die is disposed on a substrate. A first wire bond connection is formed between the interposer and semiconductor die. A second wire bond connection is formed between the interposer and substrate. A third wire bond connection is formed between the substrate and semiconductor die. An encapsulant is deposited over the substrate, semiconductor die, interposer, and SMT component. In one embodiment, the substrate is a quad flat non-leaded substrate. In another embodiment, the substrate is a land-grid array substrate, ball-grid array substrate, or leadframe.

A method of determining a sequence for creating a plurality of wire loops is provided. The method includes (a) providing workpiece data for a workpiece. The workpiece data includes (i) position data for bonding locations of the workpiece, and (ii) wire loop data for a plurality of wire loops providing interconnection between ones of the bonding locations. The method also includes (b) analyzing the workpiece data. The step of analyzing includes considering overlap conditions between ones of the plurality of wire loops, considering wire loop heights of ones of the plurality of wire loops, considering lateral bend conditions between ones of the plurality of wire loops, and considering wire loop positions for ones of the plurality of wire loops. The method also includes (c) providing a sequence of creating the plurality of wire loops in connection with the workpiece at least partially based on the results of step (b).