A converter to convert an input voltage into a regulated output current for supplying a load includes a reverse current protection diode having an anode coupled to the input voltage and a cathode, an energy storage element coupled to the cathode of the reverse current protection diode, a high side transistor coupled to the energy storage element and responsive to a high side control signal, and a low side transistor coupled to the energy storage element and responsive to a low side control signal. A controller is configured to generate the high side control signal and the low side control signal such that the low side transistor is enabled and the high side transistor is disabled during a pre-regulation interval.

A converter operable to convert an input voltage at an input node to an output voltage at an output node coupled to a load by switching on and off a transistor at a switching frequency, the converter comprising: an error amplifier circuit having a first input coupled to a reference voltage, a second input coupled to the output node through a resistive divider, a first output operable to output a control current and a second output operable to output a current equivalent to the control current; a peak current comparator circuit having a first input coupled to the second output of the error amplifier circuit, a second input and an output, the second input is coupled to the input node through an inductor; an off-time timer circuit having an input coupled to the first output of the error amplifier circuit and an output, the off-time timer circuit operable to set the switching frequency based on the control current; and a control circuit having a first input coupled to the output of the peak current comparator circuit, a second input coupled to the output of the off-time timer circuit and an output coupled to a control terminal of the transistor.

A multi-converter power supply system includes a plurality of cell converters, a common node to which an individual output terminal of each of the plurality of cell converters is connected, a current waveform signal generation circuit that generates a current waveform signal corresponding to a current waveform flowing through an individual inductor, a current average signal generation circuit that generates a current average signal by averaging temporal changes that the current waveform signal has in a switching period of a switching control circuit, and an instrumentation amplifier that receives input of a current common signal obtained from the common node and the current average signal and that generates an individual current feedback signal to be fed back to the switching control circuit.

Provided is a control circuit of a step-down converter, the control circuit including a bottom detecting circuit that asserts a turn-on signal when an output voltage of the step-down converter falls below a bottom level, an on-time generating circuit that includes a second timer circuit capable of measuring an on-time T.sub.ON in such a manner that the assertion of the turn-on signal is a trigger for the measurement, and is configured to obtain a relation of T.sub.ON=α.Math.V.sub.OUT/V.sub.IN when an input voltage of the step-down converter is defined as V.sub.IN, the output voltage is defined as V.sub.OUT, and a controllable coefficient is defined as α, a control logic that sets a high-side transistor to an on-state during the on-time T.sub.ON from the assertion of the turn-on signal and subsequently sets a low-side transistor to an on-state until the turn-on signal is asserted next, and an on-time correcting circuit that decreases the coefficient α when a switching period of the control logic is longer than a reference period, and increases the coefficient α when the switching period of the control logic is shorter than the reference period.

A half-bridge electronic device comprises, in series, a low level switch and a high level switch connected at a central point, and respectively controlled by a first and a second activation/deactivation signal. The device comprises: a first and a second synchronization system configured to interpret a variation in the voltage at the central point, respectively along a falling edge and along a rising edge, and to respectively generate a first and a second synchronization signal separate from the first; a first and a second AND type logic gate respectively combining the first synchronization signal with a first control signal and the second synchronization signal with a second control signal, in order to respectively form the first and second activation/deactivation signals.

A circuit includes an output node and an amplifier and first and second branches coupled between power supply and reference nodes. The first branch includes a first switching device coupled between a first amplifier input and the reference node, the second branch includes a second switching device coupled between the output node and a second amplifier input, and a third switching device is coupled between the power supply and output nodes. Responsive to a first voltage level on the power supply node, each of the first and second switching devices is switched off and the third switching device is switched on, and responsive to a second voltage level on the power supply node greater than the first voltage level, each of the first and second switching devices is switched on and the third switching device is switched off.

A first comparator is enabled during a period in which a wake-up signal is asserted and asserts a first detection signal indicative of a comparison result between a first feedback voltage generated by a first voltage dividing circuit and a first threshold voltage. A second comparator is always enabled and asserts a second detection signal indicative of a comparison result between a second feedback voltage V.sub.FB generated by a second voltage dividing circuit and a second threshold voltage V.sub.TH. A logic circuit generates a first pulse signal based on a first detection signal or a second detection signal, asserts the wake-up signal in a non-light load state, and negates the wake-up signal in a light load state.

Disclosed is a method and a control circuit. The method includes operating a buffer circuit (1) in a first operating mode or a second operating mode. Operating the buffer circuit (1) in the first operating mode includes buffering, by a capacitor parallel circuit including a first capacitor (11) and a second capacitor (12), power (Po) provided by a power source (3) and received by a load (4). Operating the buffer circuit (1) in the second operating mode includes supplying power to the load (4) by the second capacitor (12), and regulating a first voltage (Upn) across the second capacitor (12), wherein regulating the first voltage (Upn) comprises transferring charge from the first capacitor (11) to the second capacitor (12).

A system including: a first regulator having a first input voltage and a first output voltage; a second regulator having a second input voltage and a second output voltage; a first driver circuit coupled to the first regulator and a switch, wherein the first driver circuit is configured to drive the switch based on the first output voltage; a second driver circuit coupled to the second regulator and the switch, wherein the second driver circuit is configured to drive the switch based on the second output voltage; a driver controller coupled to the first driver circuit and the second driver circuit, wherein the driver controller is configured to select one of the first driver circuit and the second driver circuit to drive the switch based on a control signal; and a switch node coupled to the switch, wherein a switch node voltage at the switch node is a function of the switch being turned on and off.

A zero-crossing correction circuit for a switching converter having a main power switch and a synchronous power switch connected in series, can include: a detection circuit configured to detect an on-off state of a body diode of the synchronous power switch in a first time interval after the synchronous power switch is turned off and generate a detection signal; and a control and adjustment circuit configured to adjust a turn-off moment of the synchronous power switch according to an on-off state of the main power switch in a second time interval after the synchronous power switch is turned off and the detection signal