An apparatus for processing data includes a decoder configured to iteratively decode codewords in a data block representing a number of user data sectors, the codewords including user data, folded parity sector data and error correction code parity bits. The folded parity sector data includes a number of parity checks, each with multiple user data bits from each of the data sectors, and with an offset between each of the user data bits from the data sectors determined at least in part by a number of folds in the data sectors. The apparatus also includes a scheduler configured to control decoding of the codewords based at least in part on the folded parity sector data.

Some embodiments are directed to a method for controlling a check node of a NB-LDPC decoder. The check node receives d.sub.c input lists U.sub.i and delivers and delivers d.sub.c output lists V.sub.i, with i[1 . . . d.sub.c]. Each input list and output list includes n.sub.m elements and each element of the input or output lists includes a reliability value associated to a symbol of a Galois Field GF(q) with q>n.sub.m. The input elements and output elements are sorted according to the reliability values in the lists. The method is a syndrome-based method. The syndromes are sums of d.sub.c elements of input lists U.sub.i. The method includes a step of syndrome calculation, a step of decorrelation and a step for generating the output list.

Certain aspects of the present disclosure generally relate to techniques for efficient, high-performance decoding of low-density parity check (LDPC) codes, for example, by using an adjusted minimum-sum (AdjMS) algorithm, which involves approximating an update function and determining magnitudes of outgoing log likelihood ratios (LLRs). Similar techniques may also be used for decoding turbo codes. Other aspects, embodiments, and features (such as encoding technique) are also claimed and described.

In general, a minimum determination capability, adapted for determining one or more minimum values from a set of values, is provided. The minimum determination capability may enable, for a set of values, determination of a first minimum value representing a smallest value of the set of values and a second minimum value representing an approximation of a next-smallest value of the set of values. The minimum determination capability may enable, for a set of values where each of the values is represented as a respective set of bits at a respective set of bit positions, determination of a minimum value of the set of values based on a set of bitwise comparisons performed for the respective bit positions of the values.

In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.

A Low-Density Parity-Check (LDPC) decoder and a method for LDPC decoding are provided. The LDPC decoder receives a soft-decision input codeword block in which the probability of a bit being a 0 or a 1 is represented as a log-likelihood ratio (LLR). During LDPC decoding, a sequence of hardware logic units iteratively updates the soft-decision input codeword block until a valid codeword is found or a maximum number of decoding iterations is reached. Each hardware logic unit comprises a check node (CN) update logic unit and a variable node (VN) update logic unit. The CN update logic units are coupled via a closed CN path, and the VN update logic units are coupled via a closed VN path. Aspects of this LDPC decoder alleviate the global routing and energy efficiency challenges of traditional LDPC decoders, to enable multi-rate, multi-Gb/s decoding without compromising error correction performance in next-generation systems and future CMOS technology nodes.

This application is directed to compressing check node data for an electronic device. The electronic device identifies a check node corresponding to a subset of codeword symbols in a block of data and determines check node data that indicates a likelihood of the subset of codeword symbols being erroneous. A set of data bits are determined based on a value combination of data items of the check node data to uniquely identify the value combination among a set of selected value combinations according to a predefined relationship. The electronic device stores, in a memory block, the set of data bits representing the data items of the check node data of the check node. Each data item requires more data bits to represent all possible values of the respective data item than data bits of the set of data bits.

Methods, systems, and devices for wireless communications are described. A wireless communication device may implement a low-density parity-check (LDPC) code to encode and/or decode bits of a signal. The LDPC code may be defined by a base graph and a lifting scheme. The base graph may include check nodes and variable nodes. The lifting scheme may define a quantity of copies of the base graph used to generate the LDPC code and respective cyclic shifts associated with connected variable nodes and check nodes. The respective cycle shifts may be defined such that one or more cycles associated with a minimum length of the LDPC code are associated with a restriction on second degree variable nodes, nodes associated with least significant bits, or a combination thereof. Additionally, or alternatively, the respective cycle shifts may be defined such that a weighted girth of the LDPC code satisfies a threshold.

A decoder performs forward error correction based on quasi-cyclic regular column-partition low density parity check codes. A method for designing the parity check matrix reduces the number of short-cycles of the matrix to increase performance. An adaptive quantization post-processing technique further improves performance by eliminating error floors associated with the decoding. A parallel decoder architecture performs iterative decoding using a parallel pipelined architecture.

Memory systems may include a memory storage, a pre-processing checksum unit suitable for, during a first decoding iteration, receiving hard read data including channel input (Lch) sign values, and computing a checksum of the Lch sign values as a checksum_pre value, and a low-density parity-check (LDPC) decoder including an Lch memory and a checksum update unit, the LDPC decoder suitable for, during the first decoding iteration, storing the Lch sign values in the Lch memory of the LDPC decoder, receiving, with the checksum update unit, the checksum_pre value, and decoding a codeword in at least a second decoding iteration based at least in part on the checksum_pre value computed and received being a parity check on the hard read performed in the first decoding iteration.