A method for manufacturing a semiconductor device comprises: a stacking process that stacks a p-type semiconductor layer of Group III nitride containing a p-type impurity on a first n-type semiconductor layer of Group III nitride containing an n-type impurity; a p-type ion implantation process that ion-implants the p-type impurity into the p-type semiconductor layer; and a heat treatment process that performs heat treatment to activate the ion-implanted p-type impurity. The p-type ion implantation process and the heat treatment process are performed such that the p-type impurity of the p-type semiconductor layer is diffused into the n-type semiconductor layer to form a first p-type impurity containing region in at least part of the first n-type semiconductor layer and below a region of the p-type semiconductor layer into which the ion implantation has been performed.

Semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure having a buried layer at a depth of about 275 Angstroms or greater (e.g., about 500 Angstroms or greater) from a surface of the semiconductor structure. The semiconductor device includes an implanted region extending at least partially through the semiconductor structure and into the buried layer. The implanted region includes a distribution of implanted dopants of a first conductivity type extending into the buried layer. The semiconductor device includes an electrode on the implanted region. In some examples, the semiconductor structure may include an N-polar Group III-nitride semiconductor structure.

A manufacturing method of dynamic random access memory (DRAM) with low leakage current includes forming a plurality of gates within a substrate of the DRAM; forming a plurality of drain/sources within the substrate of the DRAM by a first ion implantation; and forming a plurality of lightly doped drains under all of the plurality of drain/sources or partial drain/sources of the plurality of drain/sources by a second ion implantation after the plurality of drain/sources are formed. The plurality of lightly doped drains is used for reducing a leakage current within the DRAM, and the second ion implantation has a predetermined incident angle.

A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.

Embodiments of the invention are directed to a method of forming a semiconductor device. A non-limiting example of the method includes forming a semiconductor material that includes a first type of majority carrier. A doping enhancement layer is formed over a region of the semiconductor material, wherein the doping enhancement layer includes a first type of material. A dopant is accelerated sufficiently to drive the dopant through the doping enhancement layer into the region of the semiconductor material. Accelerating the dopant through the doping enhancement layer also drives some of the first type of material from the doping enhancement layer into the region of the semiconductor material. The dopant within the region and the first type of material within the region contribute to the region having a second type of majority carrier.

There is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device comprises a process of forming a semiconductor layer that is mainly made of a group III nitride and has n-type characteristics, by crystal growth; a film formation process of forming a through film that is mainly made of an element different from an element serving as an n-type impurity relative to the group III nitride, by growth on the semiconductor layer continuous with crystal growth of the semiconductor layer; an ion implantation process of implanting a p-type impurity into the semiconductor layer across the through film by ion implantation; a heating process of heating the semiconductor layer and the through film after completion of the ion implantation process, so as to activate a region of the semiconductor layer in which the p-type impurity is ion-implanted, to a p-type semiconductor region; and a removal process of removing the through film from the semiconductor layer, after completion of the heating process. This configuration improves the surface morphology of the p-type semiconductor region formed by ion implantation.

A group III nitride semiconductor substrate may include: a p-type conduction region into which a group II element has been implanted in a depth direction of the group III nitride semiconductor substrate from a surface of the group III nitride semiconductor substrate, the p-type conduction region having p-type conductivity, wherein hydrogen has been implanted from the p-type conduction region across an n-type conduction region adjacent to the p-type conduction region in the depth direction of the group III nitride semiconductor substrate.

A vertical semiconductor apparatus includes: a gallium nitride substrate; a gallium nitride semiconductor layer on the gallium nitride substrate; a p-type impurity region in the gallium nitride semiconductor layer and having an element to function as an acceptor for gallium nitride; an n-type impurity region in the p-type impurity region and having an element to function as a donor for gallium nitride; and an electrode provided contacting a rear surface of the gallium nitride substrate. The element to function as the donor in the n-type impurity region includes: a first impurity element to enter sites of gallium atoms in the gallium nitride semiconductor layer; and a second impurity element different from the first impurity element and to enter sites of nitrogen atoms in the gallium nitride semiconductor layer. In the n-type impurity region, a concentration of the first impurity element is higher than that of the second impurity element.

A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device comprising a process of forming a p-type semiconductor layer that contains a p-type impurity and has a dislocation density of not higher than 1.010.sup.7 cm.sup.2, on an n-type semiconductor layer that contains an n-type impurity and has a dislocation density of not higher than 1.010.sup.7 cm.sup.2; an n-type semiconductor region forming process of forming an n-type semiconductor region in at least part of the p-type semiconductor layer by ion-implanting an n-type impurity into the p-type semiconductor layer and performing heat treatment to activate the ion-implanted n-type impurity; and a process of forming a trench that is recessed to pass through the p-type semiconductor layer and reach the n-type semiconductor layer. In the n-type semiconductor region forming process, a p-type impurity diffusion region in which the p-type impurity contained in the p-type semiconductor layer is diffused is formed in at least part of the n-type semiconductor layer that is located below the n-type semiconductor region.

A method for manufacturing a semiconductor device comprises forming first groove, depositing, and ion-implanting. At the step of forming the first groove, the first groove is formed in a stacked body comprising a gallium nitride (GaN)-based first semiconductor layer containing an n-type impurity and a gallium nitride (GaN)-based second semiconductor layer stacked on the first semiconductor layer and containing a p-type impurity. The first groove has a bottom portion located in the second semiconductor layer. At the depositing step, a p-type impurity is deposited on side portion and the bottom portion of the first groove. At the ion-implanting step, a p-type impurity is ion-implanted into the first semiconductor layer through the first groove.