The present application relates to a semiconductor device and a manufacturing method thereof. The method includes: obtaining a substrate, a first device region, a second device region and a high-k gate dielectric layer film being formed on the substrate; forming, on the substrate, a barrier layer structure covering the high-k gate dielectric layer film at the second device region; forming a covering layer film including a first metal element on the substrate; and diffusing the first metal element in the covering layer film towards the high-k gate dielectric layer film at the first device region using an annealing process, the barrier layer structure preventing the first metal element from being diffused towards the high-k gate dielectric layer film at the second device region; wherein the first device region and the second device region have opposite conduction types.

A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.

A semiconductor device includes a substrate, a plurality of insulators, a liner structure and a gate stack. The substrate has fins and trenches in between the fins. The insulators are disposed within the trenches of the substrate. The liner structure is disposed on the plurality of insulators and across the fins, wherein the liner structure comprises sidewall portions and a cap portion, the sidewall portions is covering sidewalls of the fins, the cap portion is covering a top surface of the fins and joined with the sidewall portions, and a maximum thickness T.sub.1 of the cap portion is greater than a thickness T.sub.2 of the sidewall portions. The gate stack is disposed on the liner structure and across the fins.

A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.

A semiconductor memory device of an embodiment includes: a first stacked body in which a plurality of first conductive layers is stacked via a first insulating layer; a second stacked body in which a plurality of second insulating layers is stacked via the first insulating layer, the second stacked body being surrounded by the first stacked body; and a pair of first plate-like portions extending in a stacking direction and in a first direction intersecting the stacking direction, the pair of first plate-like portions being disposed between the first and second stacked bodies on both sides of the second stacked body in a second direction intersecting the stacking direction and the first direction. The pair of first plate-like portions each has a first side wall facing the first stacked body and including a metal element-containing layer in contact with an end surface of the first insulating layer of the first stacked body.

A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.

A method for removing a native oxide film from a semiconductor substrate includes repetitively depositing layers of germanium on the native oxide and heating the substrate causing the layer of germanium to form germanium oxide, desorbing a portion of the native oxide film. The process is repeated until the oxide film is removed. A subsequent layer of strontium titanate can be deposited on the semiconductor substrate, over either residual germanium or a deposited germanium layer. The germanium can be converted to silicon germanium oxide by exposing the strontium titanate to oxygen.

A semiconductor memory device includes a plurality of memory cell transistors arranged along a common semiconductor layer. Each of the plurality of memory cell transistors comprises a first source/drain region and a second source/drain region formed in the common semiconductor layer; a gate stack formed on a portion of the common semiconductor layer between the first source/drain region and the second source/drain region; and an electrical floating portion in the portion of the common semiconductor layer, a charge state of the electrical floating portion being adapted to adjust a threshold voltage and a channel conductance of the memory cell transistor. The plurality of memory cell transistors connected in series with each other along the common semiconductor layer provide a memory string.