A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

Methods are provided for planarizing a patterned substrate in a spatial atomic layer processing system comprising a rotating platen. The patterned substrate may generally include features having higher regions and lower regions. To planarize the patterned substrate, or reduce a height differential between the higher and lower regions, a selective atomic layer etching (ALE) process is disclosed to preferentially form a modified layer on the higher regions of the features by exposing a surface of the patterned substrate to a precursor gas while the rotating platen spins at a high rotational speed. By preferentially forming the modified layer on the higher regions of the features, and subsequently removing the modified layer, the selective ALE process described herein preferentially etches the higher regions of the features to lessen the height differential between the higher and lower regions until a desired planarization of the features is achieved.

Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

A substrate processing method includes: preparing a substrate having a recess and a first film embedded in the recess; and removing the first film by etching while forming a second film so as to cover the recess from which the first film was removed by supplying a processing gas to the substrate, the processing gas including a gas contributing to film formation and a gas contributing to the etching.

A method and structure for forming a via-first metal gate contact includes depositing a first dielectric layer over a substrate having a gate structure with a metal gate layer. An opening is formed within the first dielectric layer to expose a portion of the substrate, and a first metal layer is deposited within the opening. A second dielectric layer is deposited over the first dielectric layer and over the first metal layer. The first and second dielectric layers are etched to form a gate via opening. The gate via opening exposes the metal gate layer. A portion of the second dielectric layer is removed to form a contact opening that exposes the first metal layer. The gate via and contact openings merge to form a composite opening. A second metal layer is deposited within the composite opening, thus connecting the metal gate layer to the first metal layer.

An object of the present invention is to improve a substrate processing apparatus using the CARE method. The present invention provides a substrate processing apparatus for polishing a processing target region of a substrate by bringing the substrate and a catalyst into contact with each other in the presence of processing liquid. The substrate processing apparatus includes a substrate holding unit configured to hold the substrate, a catalyst holding unit configured to hold the catalyst, and a driving unit configured to move the substrate holding unit and the catalyst holding unit relative to each other with the processing target region of the substrate and the catalyst kept in contact with each other. The catalyst is smaller than the substrate.

A semiconductor device includes: a protruding conductive structure that protrudes to a height from a first surface of the semiconductor device; and a first passivation layer, the first passivation layer overlaying the protruding conductive structure by a first thickness, the first passivation layer overlaying the first surface by a second thickness greater than the first thickness, wherein the first passivation layer is planar at a top surface over the first thickness and the second thickness.

Provided is a method of manufacturing a semiconductor device including: providing a substrate having a memory cell region and a logic region; forming a plurality of stack structures on the substrate in the memory cell region; forming a polysilicon layer to cover the plurality of stack structures and the substrate in the logic region; performing a chemical-mechanical polishing (CMP) process on the polysilicon layer to expose top surfaces of the plurality of stack structures; and after performing the CMP process, patterning the polysilicon layer to form an erase gate between adjacent two stack structures and form a logic gate on the substrate in the logic region, wherein the logic gate has a topmost top surface lower than a topmost top surface of the erase gate.

A polishing composition for use in polishing an object to be polished, which comprises abrasive grains, a dispersing medium, and an additive, wherein the abrasive grains are surface-modified, the additive is represented by the following formula 1: ##STR00001##
wherein in the formula 1, X.sub.1 is O or NR.sub.4, X.sub.2 is a single bond or NR.sub.5, R.sub.1 to R.sub.5 are each independently a hydrogen atom; a hydroxy group; a nitro group; a nitroso group; a C.sub.1-4 alkyl group optionally substituted with a carboxyl group, an amino group, or a hydroxy group; or CONH.sub.2; with the proviso that R.sub.2 and R.sub.5 may form a ring; when X.sub.2 is a single bond, R.sub.3 is not a hydrogen atom, or R.sub.1 to R.sub.3 are not a methyl group; and when X.sub.2 is NR.sub.5 and three of R.sub.1 to R.sub.3 and R.sub.5 are a hydrogen atom, the other one is not a hydrogen atom or a methyl group; and a pH is 5.0 or less. According to the present invention, a polishing composition capable of polishing not only polycrystalline silicon but also a silicon nitride film at high speed and also suppressing a polishing speed of a silicon oxide film is provided.

A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.