In one embodiment, a semiconductor wafer includes a first substrate, a first insulator provided on the first substrate, and a plurality of first pads provided in the first insulator. The wafer further includes a second insulator provided on the first insulator, a plurality of second pads provided on the first pads in the second insulator, a stacked film alternately including a plurality of first insulating layers and a plurality of second insulating layers provided in the second insulator, and a second substrate provided on the second insulator. Furthermore, the first insulator and the second insulator are connected to each other between an edge face of the first insulator and an edge face of the second insulator, and the second insulator intervenes between the first insulator and the stacked film at the edge faces of the first and second insulators.

Methods process microelectronic workpieces with inverse extreme ultraviolet (EUV) patterning processes. In part, the inverse patterning techniques are applied to reduce or eliminate defects experienced with conventional EUV patterning processes. The inverse patterning techniques include additional process steps as compared to the conventional EUV patterning processes, such as an overcoat process, an etch back or planarization process, and a pattern removal process. In addition, further example embodiments combine inverse patterning techniques with line smoothing treatments to reduce pattern roughness and achieve a target level of line roughness. By using this additional technique, line pattern roughness can be significantly improved in addition to reducing or eliminating microbridge and/or other defects.

A method of forming a reversed pattern including: a step of forming a resist film on a substrate using a photosensitive composition having an A value of 0.14 or more, which is determined by Expression (1); a step of exposing the resist film to light; a step of developing the exposed resist film to form a resist pattern; a step of applying a pattern reversal film forming composition such that the resist pattern is coated and thereby forming a pattern reversal film; a step of performing etch-back on the pattern reversal film and exposing a surface of the resist pattern to light; and a step of removing the resist pattern to form the reversed pattern,

A=([H]×0.04+[C]×1.0+[N]×2.1+[O]×3.6+[F]×5.6+[S]×0.04+[I]×39.5)/([H]×1+[C]×12+[N]×14+[O]×16+[F]×19+[S]×32+[I]×127)  Expression (1):

Semiconductor device and transistor are provided. The semiconductor device includes a plurality of first fin structures formed on a substrate, each first fin structure having a first width along a first direction perpendicular to a length direction of the first fin structure; a plurality of second fin structures, each formed on a first fin structure and including a first region located on the first fin structure and a second region located on the first region, the first region having a second width along the first direction, and the second region having a third width along the first direction; a first isolation layer, formed on the substrate and between adjacent first fin structures and adjacent second fin structures; and a second isolation layer formed on the first region and between a bottom portion of sidewall surfaces of each second region and the first isolation layer.

A method is provided for forming a device. The method includes forming a trench that exposes a source/drain (S/D) feature, wherein the S/D feature is separated from a metal gate structure (MG) by a gate spacer. The method further includes removing the gate spacer to form an air gap and forming a first dielectric layer in the trench, wherein the first dielectric layer partially fills the air gap. The method also includes forming a second dielectric layer over the first dielectric layer in the trench and forming a S/D contact over the S/D feature and the second dielectric layer, wherein the second dielectric layer is different from the first dielectric layer. After forming the S/D contact, the first dielectric layer is removed to extend the air gap; and after removing the first dielectric layer, a third dielectric layer is formed to seal the air gap.

Methods and apparatuses for selectively growing metal-containing hard masks are provided herein. Methods include providing a substrate having a pattern of spaced apart features, each feature having a top horizontal surface, filling spaces between the spaced apart features with carbon-containing material to form a planar surface having the top horizontal surfaces of the features and carbon-containing material, selectively depositing a metal-containing hard mask on the top horizontal surfaces of the features relative to the carbon-containing material, and selectively removing the carbon-containing material relative to the metal-containing hard mask and features.

A method of fabricating a semiconductor device includes forming a semiconductor fin structure over a substrate, where the semiconductor fin structure includes a plurality of semiconductor fins and defines trenches among the semiconductor fins, and forming a dielectric fin structure having a plurality of dielectric fins. Forming the dielectric fin structure includes filling the trenches with a first dielectric material layer and a second dielectric material layer over the first dielectric material layer, the second dielectric material layer having a composition different from that of the first dielectric material layer, removing a portion of the second dielectric material layer to form a recess, and filling the recess with a third dielectric material layer, the third dielectric material layer having the same composition as the first dielectric material layer.

Techniques for planarization of dielectric topography that stop in dielectric are provided. In one aspect, a method for planarization includes: depositing a first dielectric onto a wafer having a surface topography with peaks and valleys; depositing a second, different dielectric onto the first dielectric; and polishing the second dielectric down to the first dielectric to form a planar surface at an interface between the first dielectric and the second dielectric. Optionally, a follow-up CMP or etch can be performed using a ˜1:1 selective polish or etch to completely remove the second dielectric and an equivalent amount of the first dielectric to form a planar surface devoid of the peaks and valleys in the first dielectric. A device structure formed by the present techniques is also provided.

A semiconductor manufacturing apparatus includes a first top ring that is rotatable and configured to hold a wafer, a first turntable that is rotatable and has a polishing pad for performing polishing of a film formed on the wafer, a sound measuring unit (sensor) that measures a first sound generated during the polishing, and a first calculation unit (controller) that calculates a polishing amount of the film based on a first sound pressure of the first sound, a polishing amount per unit time of the polishing, and a time of the polishing.

A method of forming a gate includes the following steps. A gate structure is formed on a substrate. An etch stop layer is formed on the gate structure and the substrate. A dielectric layer is formed to cover the etch stop layer. The dielectric layer is planarized to form a planarized top surface of the dielectric layer and expose a portion of the etch stop layer on the gate structure. An oxygen containing treatment is performed to form an oxygen containing layer on the exposed etch stop layer. A deposition process is performed to form an oxide layer covering the planarized top surface of the dielectric layer and the oxygen containing layer.