A first dielectric layer made of a first dielectric material is deposited over a semiconductor substrate. A buffer layer is then deposited on an upper surface of the first dielectric layer. A trench is opened to extend through the buffer layer and the first dielectric layer. A second dielectric layer made of a second dielectric material is the deposited in a conformal manner on the buffer layer and filling the trench. Chemical mechanical polishing of the second dielectric layer is performed to remove overlying portions of the second dielectric layer with the buffer layer being used as a polish stop. After removing the buffer layer, the first dielectric layer and the second dielectric material filling the trench form a pre-metallization dielectric layer having a substantially planar upper surface.

A method of manufacturing an integrated circuit device is provided. A first feature, which has a first susceptibility to damage by chemical mechanical processing (CMP), is formed at a first height as measured from an upper surface of the substrate. A second feature, which has a second susceptibility to damage by the CMP, is formed at a second height as measured from the upper surface of the substrate and is laterally spaced from the first feature by a recess. The second height is greater than the first height, and the second susceptibility is less than the first susceptibility. A sacrificial coating is formed in the recess over an uppermost surface of the first feature. CMP is performed to remove a first portion of the sacrificial coating and expose an upper surface of the second feature while leaving a second portion of the sacrificial coating in place over the first feature.

Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

A method of forming a uniform self-aligned low-k layer with a large process window for inserting a memory array with pillar/convex topography and the resulting device are provided. Embodiments include forming a substrate with a first region and a second region; forming a first low-K layer over the substrate; forming an oxide layer over the first low-K layer; forming a spacer over the oxide layer; etching the spacer to expose the oxide layer in the first region; removing the oxide layer and a portion of the first low-K layer in the first region and a portion of the oxide layer and a portion of the spacer in the second region; removing the spacer in the second region; cleaning the first low-K layer and the oxide layer, a triangular-like shaped portion of the oxide layer remaining; and forming a second low-K layer over the substrate.

A method of manufacturing a semiconductor device includes forming a via including a first conductive material on an inner wall of a trench on a substrate. The method further includes forming a first insulating interlayer on the substrate. The first insulating interlayer covers the via and partially fills the trench, and the first insulating interlayer has a non-flat upper surface. The method further includes forming a polishing stop layer on the first insulating interlayer, forming a second insulating interlayer on the polishing stop layer, in which the second insulating interlayer fills a remaining portion of the trench, planarizing the second insulating interlayer until the polishing stop layer is exposed, and etching the polishing stop layer and the first and second insulating interlayers using a dry etching process until remaining portions of the polishing stop layer except for a portion of the polishing stop layer in the trench are removed.

A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.

In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

The present disclosure provides a method for planarization. The method includes providing a substrate having a top surface and a trench recessed from the top surface; coating a sensitive material layer on the top surface of the substrate, wherein the sensitive material layer fills in the trench; performing an activation treatment to the sensitive material layer so that portions of the material layer are chemically changed; and performing a wet chemical process to the sensitive material layer so that top portions of the sensitive material layer above the trench are removed, wherein remaining portions of the sensitive material layer have top surfaces substantially coplanar with the top surface of the substrate.

A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

The present disclosure discloses a manufacturing method for a semiconductor apparatus, and relates to the field of semiconductor technologies. Forms of the method include: providing a semiconductor structure, where the semiconductor structure includes: a substrate and an interlayer dielectric layer on the substrate, where the interlayer dielectric layer has an opening for forming a gate; depositing a gate metal layer on the semiconductor structure to fill the opening, where the gate metal layer contains impurity; forming an impurity adsorption layer on the gate metal layer; performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer; and removing the impurity adsorption layer after the first annealing treatment is performed. The present disclosure may reduce impurity in the gate metal layer, thereby improving contact resistance of the gate and improving device performance.