A chemical mechanical polishing composition for polishing a substrate having copper, barrier, and dielectric layers includes a water based liquid carrier, cationic silica abrasive particles dispersed in the liquid carrier, and a triazole compound, wherein the polishing composition has a pH of greater than about 6 and the cationic silica abrasive particles have a zeta potential of at least 10 mV. The triazole compound is not benzotriazole or a benzotriazole compound. A method for chemical mechanical polishing a substrate including copper, barrier, and dielectric layers includes contacting the substrate with the above described polishing composition, moving the polishing composition relative to the substrate, and abrading the substrate to remove a portion of the copper, barrier, and dielectric layers from the substrate and thereby polish the substrate.

Provided is an integrated circuit including a substrate, a plurality of first gate structures, a protective layer, a second gate structure, a source region, and a drain region. The substrate has a cell region and a peripheral region. The plurality of first gate structures are disposed in the cell region. A top surface and a sidewall of the plurality of first gate structures are covered by the protective layer. The second gate structure is disposed in the peripheral region. The source region and the drain region are disposed on the both side of the second gate structure. A manufacturing method of the integrated circuit is also provided.

A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate and two epitaxial structures over the substrate. Each of the semiconductor nanostructures is between the epitaxial structures, and the epitaxial structures are p-type doped. The semiconductor device structure also includes a gate stack wrapping around the semiconductor nanostructures. The semiconductor device structure further includes a dielectric stressor structure between the gate stack and the substrate. The epitaxial structures extend exceeding a top surface of the dielectric stressor structure.

A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.

According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.

A semiconductor structure and a method of fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate; a metal gate structure on the substrate; and a spacer next to the metal gate structure having a skirting part extending into the metal gate structure and contacting the substrate. The metal gate structure includes a high-k dielectric layer and a metal gate electrode on the high-k dielectric layer.

A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.

A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

A polishing composition for use in polishing an object to be polished, which comprises abrasive grains, a dispersing medium, and an additive, wherein the abrasive grains are surface-modified, the additive is represented by the following formula 1:

##STR00001##

wherein in the formula 1, X.sub.1 is O or NR.sub.4, X.sub.2 is a single bond or NR.sub.5, R.sub.1 to R.sub.5 are each independently a hydrogen atom; a hydroxy group; a nitro group; a nitroso group; a C.sub.1-4 alkyl group optionally substituted with a carboxyl group, an amino group, or a hydroxy group; or CONH.sub.2; with the proviso that R.sub.2 and R.sub.5 may form a ring; when X.sub.2 is a single bond, R.sub.3 is not a hydrogen atom, or R.sub.1 to R.sub.3 are not a methyl group; and when X.sub.2 is NR.sub.5 and three of R.sub.1 to R.sub.3 and R.sub.5 are a hydrogen atom, the other one is not a hydrogen atom or a methyl group; and a pH is 5.0 or less. According to the present invention, a polishing composition capable of polishing not only polycrystalline silicon but also a silicon nitride film at high speed and also suppressing a polishing speed of a silicon oxide film is provided.

A method of forming a memory device is provided. In some embodiments, a memory cell is formed over a substrate, and a sidewall spacer layer is formed along the memory cell. A lower etch stop layer is formed on the sidewall spacer layer, and an upper dielectric layer is formed on the lower etch stop layer. A first etching process is performed to etch back the upper dielectric layer using the lower etch stop layer as an etch endpoint.