A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and a buried oxide (BOX) layer over the at least one device layer. A polymer layer is disposed over the BOX layer, wherein the polymer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10.sup.3 Ohm-cm.

A replacement metal gate transistor structure and method with thin silicon nitride sidewalls and with little or no high-k dielectric on the vertical sidewalls of the replacement gate transistor trench.

A chemical mechanical polishing pad is provided, comprising: a chemical mechanical polishing layer having a polishing surface; wherein the chemical mechanical polishing layer is formed by combining (a) a poly side (P) liquid component, comprising: an amine-carbon dioxide adduct; and, at least one of a polyol, a polyamine and a alcohol amine; and (b) an iso side (I) liquid component, comprising: polyfunctional isocyanate; wherein the chemical mechanical polishing layer has a porosity of ≧10 vol %; wherein the chemical mechanical polishing layer has a Shore D hardness of <40; and, wherein the polishing surface is adapted for polishing a substrate. Methods of making and using the same are also provided.

The present application relates to a block copolymer and uses thereof. The present application can provide a block copolymer—which exhibits an excellent self-assembling property and thus can be used effectively in a variety of applications—and uses thereof.

An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a polymer coating, CMP to form a planar surface, then plasma etching to effectuate a planar recessing of the polymer coating. The material can be recessed together with the polymer coating, or subsequently with the recessed polymer coating providing a mask. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The polymer can be a photoresist. The polymer can be provided with suitable adhesion and uniformity for the CMP process through a two-step baking process and by exhausting the baking chamber from below the substrate.

Forming a semiconductor arrangement includes non-destructively determining a first spacer height of a first sidewall spacer adjacent a dummy gate and a second spacer height of a second sidewall spacer adjacent the dummy gate based upon a height of a photoresist as measured using optical critical dimension (OCD) spectroscopy. When the photoresist is sufficiently uniform, a hard mask etch is performed to remove a hard mask from the dummy gate and to remove portions of sidewall spacers of the dummy gate. A gate electrode is formed between the first sidewall spacer and the second sidewall spacer to form a substantially uniform gate. Controlling gate formation based upon photoresist height as measured by OCD spectroscopy provides a non-destructive manner of promoting uniformity.

The disclosure includes forming a SiGe region on two adjacent fin structures and a SiP region on the fin structures adjacent to the SiGe region; forming SDB trenches; forming SiN plugs over the SDB trenches to make top-sealed hollow SDB trenches. The process for forming SDB trenches adds no additional cost, and the process is compatible with existing process flow. The SiN plugs are configured to seal the SDB trenches from top, such that the SDB trenches are filled with air and do not need to be thermally annealed. The advantage includes low fin loss in the annealing oxidation process and better controlled uniformity of the SDB trenches. Air in the SDB trenches reduces the parasitic capacitance of adjacent contacts, therefore and it is conducive to improving the device speed.

The present invention is to form an organic film on a substrate having a pattern formed on a front surface thereof and configured to: apply an organic material onto the substrate; then thermally treat the organic material to form an organic film on the substrate; and then perform ultraviolet irradiation processing on the organic film to remove a surface of the organic film down to a predetermined depth, thereby appropriately and efficiently form the organic film on the substrate.

CMP pad dressers having leveled tips and associated methods are provided. In one aspect, for example, a composite conditioner can include a base plate and a plurality of polishing units secured to a surface of the base plate by an adhesive layer, where each polishing unit includes a plurality of polishing tips secured in a binding layer. Additionally, a height difference between a first highest polishing tip and a second highest polishing tip is less than or equal to about 10 μm, a height difference between the first highest polishing tip and a tenth highest polishing tip is less than or equal to about 20 μm, and a height difference between the first highest polishing tip and a 100th highest polishing tip is less than or equal to about 40 μm. Furthermore, the first highest polishing tip protrudes from the binding layer to a height of greater than or equal to about 50 μm.

A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.