The invention relates to cerium based core-shell particles having a core of cerium oxide optionally doped with at least one metal (M) and a shell consisting of a plurality of nanoparticles of cerium oxide optionally doped with at least one metal (M′), which can be the same or different from metal (M), formed on the surface of the core particle. The invention also relates to dispersions thereof in a liquid medium, to a process for producing the same and to the use of these particles and dispersions in polishing applications such as chemical mechanical polishing.

Provided are a composition for chemical mechanical polishing and a method for polishing allowing a tungsten film- or silicon nitride film-containing semiconductor substrate to be polished at a high speed, while also enabling a reduction in the occurrence of a surface defect in the polished face after polishing. A composition for chemical mechanical polishing according to the present invention comprises (A) abrasive grains containing titanium nitride and (B) a liquid medium, wherein the absolute value of the zeta-potential of said (A) component in the composition for chemical mechanical polishing is 8 mV or higher.

A slurry containing abrasive grains and a liquid medium, the abrasive grains including first particles and second particles being in contact with the first particles, the first particles containing ceria, the first particles having a negative zeta potential, the second particles containing a hydroxide of a tetravalent metal element, and the second particles having a positive zeta potential.

A method of detecting a polishing endpoint includes storing a plurality of library spectra, measuring a sequence of spectra from the substrate in-situ during polishing, and for each measured spectrum of the sequence of spectra, finding a best matching library spectrum from the plurality of library spectra to generate a sequence of best matching library spectra. Each library spectrum has a stored associated value representing a degree of progress through a polishing process, and the stored associated value for the best matching library spectrum is determined for each best matching library spectrum to generate a sequence of values representing a progression of polishing of the substrate. The sequence of values is compared to a target value, and a polishing endpoint is triggered when the sequence of values reaches the target value.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

Provided is a new cerium-based particle and a polishing slurry composition including the same. The new cerium-based particle may include a self-assembly of fine particles and an organic material.

A method of manufacturing a semiconductor device includes forming a gate oxide layer on a substrate, where the substrate includes a high voltage region and a low voltage region. The gate oxide layer is disposed in the high voltage region. Wet etching is performed on the gate oxide layer to reduce a thickness of the gate oxide layer. Multiple trenches are formed around the high voltage region in the substrate, where forming the trenches includes removing an edge of the gate oxide layer to make the thickness of the gate oxide layer uniform. An insulating material is filled in the trenches to form multiple shallow trench isolation structures, where an upper surface of the shallow trench isolation structures close to the edge of the gate oxide layer is coplanar with an upper surface of the gate oxide layer.

The current disclosure describes techniques of protecting a metal interconnect structure from being damaged by subsequent chemical mechanical polishing processes used for forming other metal structures over the metal interconnect structure. The metal interconnect structure is receded to form a recess between the metal interconnect structure and the surrounding dielectric layer. A metal cap structure is formed within the recess. An upper portion of the dielectric layer is strained to include a tensile stress which expands the dielectric layer against the metal cap structure to reduce or eliminate a gap in the interface between the metal cap structure and the dielectric layer.

A thin film transistor includes an active layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, a capping layer filling a thickness difference between the first portion and the second portion and arranged on the first portion, a gate insulating layer arranged on the capping layer, a gate electrode on the active layer, wherein the gate insulating layer and the capping layer are disposed between the gate electrode and the active layer, and a source electrode and a drain electrode connected to the active layer.