The present disclosure is a composition for a semiconductor process applied to a polishing process of a semiconductor wafer and, more specifically, to a semiconductor process involving a polishing process of a semiconductor wafer, wherein the composition includes abrasive particles, and the zeta potential of the abrasive particles is −50 mV to −10 mV at a pH of 6, and the zeta potential change rate represented by Equation 1 below is 6 mV to 30 mV: [Equation 1] Zeta potential change rate (mV/pH)=|(Z6−Z5)/(p6−p5)| where p6 denotes pH 6, p5 denotes pH 5, Z6 denotes a zeta potential at the pH 6, and Z5 denotes a zeta potential at the pH 5.

A CMP slurry composition for polishing a tungsten pattern wafer and a method of polishing a tungsten pattern wafer, the composition including a solvent, the solvent including a polar solvent or a non-polar solvent; an abrasive agent; and an oxidizing agent, wherein the abrasive agent includes silica modified with an amino silane that includes three nitrogen atoms.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Gate patterns are formed on a semiconductor layer and a conductive film is formed on the semiconductor layer so as to cover the gate patterns. By performing a polishing process to the conductive film and patterning the polished conductive film, pad layers are formed between the gate patterns via sidewall spacers.

A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

Embodiments provide a polishing composition for a semiconductor process facilitating the formation of a microcircuit pattern and minimizing the generation of defects and scratches and a method of preparing a polished article using the same.

Embodiments provide a polishing composition for a semiconductor process, in which the absorbance ratio of a group having a specific size of particle diameter compared to the overall average particle size (D.sub.50) is a predetermined ratio or less with respect to the absorbance of a group having a particle diameter more than 0.5 times and 2.5 times or less the overall average particle size.

Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.

Provided is a semiconductor device including a substrate, multiple first gate structures, and a protective structure. The substrate includes a first region and a second region. The first gate structures are disposed on the substrate in the first region. The protective structure conformally covers a sidewall of one of the first gate structures adjacent to the second region. The protective structure includes a lower portion and an upper portion disposed on the lower portion. The lower portion and the upper portion have different dielectric materials. A method of forming a semiconductor device is also provided.

A method of performing a chemical mechanical planarization (CMP) process includes holding a wafer by a retainer ring attached to a carrier, pressing the wafer against a first surface of a polishing pad, the polishing pad rotating at a first speed, dispensing a slurry on the first surface of the polishing pad, and generating vibrations at the polishing pad.

Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.