A method for fabricating a semiconductor device includes providing a substrate including a cell region and a core/peripheral region around the cell region, forming a gate insulating film on the substrate of the core/peripheral region, forming a first conductive film of a first conductive type on the gate insulating film, forming a diffusion blocking film within the first conductive film, the diffusion blocking film being spaced apart from the gate insulating film in a vertical direction, after forming the diffusion blocking film, forming an impurity pattern including impurities within the first conductive film, diffusing the impurities through a heat treatment process to form a second conductive film of a second conductive type and forming a metal gate electrode on the second conductive film, wherein the diffusion blocking film includes helium (He) and/or argon (Ar).

Approaches herein decrease nanosheet gate length variations by implanting a gate layer material with ions prior to etching. A method may include forming a dummy gate structure over a nanosheet stack, the dummy gate structure including a hardmask atop a gate material layer, and removing a portion of the hardmask to expose a first area and a second area of the gate material layer. The method may further include implanting the dummy gate structure to modify the first and second areas of the gate material layer, and etching the first and second areas of the gate material layer to form a treated layer along a sidewall of a third area of the gate material layer, wherein the third area is beneath the hardmask.

A method for forming a semiconductor structure includes: providing a substrate, a gate dielectric layer and an undoped polycrystalline silicon layer sequentially stacked; performing a thermal doping process, and doping first doping ions in the polycrystalline silicon layer; and performing an ion implantation process, and doping second doping ions in a preset region of the polycrystalline silicon layer. The preset region is spaced at a preset distance from a surface of the polycrystalline silicon layer away from the gate dielectric layer in a direction perpendicular to a surface of the substrate.

A semiconductor structure includes a substrate, a pair of first fins extending from the substrate, a pair of second fins extending from the substrate, an isolation feature over the substrate and separating bottom portions of the first and the second fins, a pair of first epitaxial semiconductor features over the pair of first fins respectively, a pair of second epitaxial semiconductor features over the pair of second fins respectively, and a first dielectric feature sandwiched between and separating the pair of first epitaxial semiconductor features. The pair of second epitaxial semiconductor features merge with each other.

An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.

A non-volatile memory device and its manufacturing method are provided. The method includes the following steps. A plurality of isolation structures are formed in a substrate. A first polycrystalline silicon layer is formed in the substrate and between two adjacent isolation structures. A first implantation process is performed to implant a first dopant into the first polycrystalline silicon layer and the isolation structures. A portion of each of the isolation structures is partially removed, and the remaining portion of each of the isolation structures has a substantially flat top surface. An annealing process is performed after partially removing the isolation structures to uniformly diffuse the first dopant in the first polycrystalline silicon layer. A dielectric layer is formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer is formed on the dielectric layer.

A solar cell includes: a semiconductor substrate which includes a first principal surface and a second principal surface; a first semiconductor layer of the first conductivity type disposed above the first principal surface; and a second semiconductor layer of a second conductivity type disposed below the second principal surface. The semiconductor substrate includes: a first impurity region of the first conductivity type; a second impurity region of the first conductivity type disposed between the first impurity region and the first semiconductor layer; and a third impurity region of the first conductivity type disposed between the first impurity region and the second semiconductor layer. A concentration of an impurity in the second impurity region is higher than a concentration of the impurity in the third impurity region, and the concentration of the impurity in the third impurity region is higher than a concentration of the impurity in the first impurity region.

The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern. The present disclosure improves the accuracy of pattern transfer.