The present disclosure describes a semiconductor device with substantially uniform gate regions and a method for forming the same. The method includes forming a fin structure on a substrate, the fin structure including one or more nanostructures. The method further includes removing a portion of the fin structure to expose an end of the one or more nanostructures and etching the end of the one or more nanostructures with one or more etching cycles. Each etching cycle includes purging the fin structure with hydrogen fluoride (HF), etching the end of the one or more nanostructures with a gas mixture of fluorine (F.sub.2) and HF, and removing an exhaust gas mixture including an etching byproduct. The method further includes forming an inner spacer in the etched end of the one or more nanostructures.

A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.

The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

The present disclosure provides a method for fabricating a semiconductor structure, including forming a dielectric layer over a first region and a second region of a substrate, wherein the second region is adjacent to the first region, increasing a thickness of the dielectric layer in the first region, including forming an oxygen capturing layer over the dielectric layer in the first region, including forming the oxygen capturing layer over the first region and the second region, and removing the oxygen capturing layer over the second region with a mask layer, performing an oxidizing operation from a top surface of the oxygen capturing layer to increase oxygen concentration of the oxygen capturing layer, removing the oxygen capturing layer over the first region, and forming a gate structure over the dielectric layer.

Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

The present disclosure describes a method for forming (i) input/output (I/O) fin field effect transistors (FET) with polysilicon gate electrodes and silicon oxide gate dielectrics integrated and (ii) non-I/O FETs with metal gate electrodes and high-k gate dielectrics. The method includes depositing a silicon oxide layer on a first region of a semiconductor substrate and a high-k dielectric layer on a second region of the semiconductor substrate; depositing a polysilicon layer on the silicon oxide and high-k dielectric layers; patterning the polysilicon layer to form a first polysilicon gate electrode structure on the silicon oxide layer and a second polysilicon gate electrode structure on the high-k dielectric layer, where the first polysilicon gate electrode structure is wider than the second polysilicon gate electrode structure and narrower than the silicon oxide layer. The method further includes replacing the second polysilicon gate electrode structure with a metal gate electrode structure.

Semiconductor devices and methods of manufacturing are presented wherein a gate dielectric is treated within an analog region of a semiconductor substrate. The gate dielectric may be treated with a plasma exposure and/or an annealing process in order to form a recovered region of the gate dielectric. A separate gate dielectric is formed within a logic region of the semiconductor substrate, and a first gate electrode and second gate electrode are formed over the gate dielectrics.

A semiconductor device with different isolation structures and a method of fabricating the same are disclosed. The a method includes forming first and second fin structures on a substrate, forming a dummy fin structure on the substrate and between the first and second fin structures, forming a polysilicon structure on the dummy fin structure, forming source/drain regions on the first and second fin structures, and replacing the polysilicon structure with a dummy gate structure. A top portion of the dummy gate structure is formed wider than a bottom portion of the dummy gate structure.