The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.

The present disclosure relates to a semiconductor device, an operation method of a semiconductor device, and a manufacturing method of a semiconductor device which are capable of minimizing influence of a gate length variation on a circuit characteristic and increasing a good product ratio (yield) in a product sorting test. A ring oscillator configured such that the plurality of inverters is connected in a ring-like form, and gate capacitors of the transistors are connected to respective output terminals of the plurality of inverters as a load capacitor outputs an oscillating signal, the ring oscillator is configured with a plurality of transistors having the same gate length, and at least two or more ring oscillators including a plurality of transistors having different gate lengths are configured. At the time of product test, the gate length is calculated on the basis of frequencies of oscillating signals of a plurality of ring oscillators, and a back bias is applied in accordance with a correction value corresponding to the calculated gate length, and an operation is performed. The present disclosure can be applied to semiconductor devices.

An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of M.sub.x layer power interconnects coupled to a first voltage, a first set of M.sub.x layer interconnects, a second set of M.sub.x layer power interconnects coupled to a second voltage source, and a second set of M.sub.x layer interconnects. The first set of endcap cells includes first and second sets of M.sub.x+1 layer interconnects. The first set of M.sub.x+1 layer interconnects is coupled to the first set of M.sub.x layer power interconnects and to the second set of M.sub.x layer interconnects to provide a first set of decoupling capacitors. The second set of M.sub.x+1 layer interconnects is coupled to the second set of M.sub.x layer power interconnects and to the first set of M.sub.x layer interconnects to provide a second set of decoupling capacitors.