A first PMOS transistor is defined by a gate electrode extending along a first gate electrode track. A second PMOS transistor is defined by a gate electrode extending along a second gate electrode track. A first NMOS transistor is defined by a gate electrode extending along the second gate electrode track. A second NMOS transistor is defined by a gate electrode extending along a third gate electrode track. The gate electrodes of the first PMOS transistor and the first NMOS transistor are electrically connected to a first gate node. The gate electrodes of the second PMOS transistor and the second NMOS transistor are electrically connected to a second gate node. Each of the first PMOS transistor, the first NMOS transistor, the second PMOS transistor, and the second NMOS transistor has a respective diffusion terminal electrically connected to a common output node.

The present invention relates to IC chips containing a mixture of standard cells obtained from an original set of design rules and enhanced standard cells that are a variant of the original set of design rules and methods for making the same.

Disclosed are standard cells, transistors, and methods for fabricating the same. In an aspect, a transistor includes a drain and a source each including a first drain/source silicide layer on a frontside surface of the drain/source and a second drain/source silicide layer on a backside surface of the drain/source. The first drain silicide layer is coupled to a first drain contact structure or the second drain silicide layer is coupled to a second drain contact structure. The first source silicide layer is coupled to a first source contact structure or the second source silicide layer is coupled to a second source contact structure. A gate structure is disposed between the source and the drain. A channel is at least partially enclosed by the gate structure and disposed between the source and the drain and is recessed from the backside surfaces of the source and drain.

A semiconductor device according to embodiments includes: a first semiconductor layer having a first source region, a first drain region, and a first channel region; a second semiconductor layer having a second source region, a second drain region, and a second channel region; and a gate electrode that is formed to cover the first channel region and the second channel region with a gate insulating film interposed. The semiconductor device includes a first CMOS circuit and a second CMOS circuit each formed of the combination of a first conductive type MOS having the first semiconductor layer and a second conductive type MOS having the second semiconductor layer. The first semiconductor layer is stacked in a (2n?1).sup.th layer. The second semiconductor layer is stacked in a 2n.sup.th layer (1?n?N, N?2, and n and N are integers).

Disclosed are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate including a cell disposing region and a first block border region, a plurality of gate electrodes on the cell disposing region and extending to the first block border region in a first direction to be parallel to each other, the gate electrodes including a first and second gate electrode, which are adjacent to each other, and a first connection structure on the first block border region, wherein the first connection structure is configured to physically connect the first and second gate electrodes to each other.

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first M.sub.x layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M.sub.x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M.sub.x layer interconnects are parallel. The MOS device further includes a first M.sub.x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The MOS device further includes a second M.sub.x+1 layer interconnect extending in the second direction. The second M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The second M.sub.x+1 layer interconnect is parallel to the first M.sub.x+1 layer interconnect.

Integrated circuits and related logic circuits and structures employing VTFET logic devices. In particular, during middle-of-line (MOL) processing, method steps are employed for forming two-level MOL contact connector structures below first (M1) metallization level wiring formed during subsequent BEOL processing. Using damascene and subtractive metal etch techniques, respective MOL contact connector structures at two levels are formed with a second level above a first level contact. These contact connector structures at two levels below M1 metallization level can provide cross-connections to VTFET devices of logic circuits that enable increased scaling of the logic circuit designs, e.g., especially for multiplexor circuit layouts due to wiring access. The flexible MOL cross-connections made below M1 metallization level provides for much improved M1 and M2 wirability and enable semiconductor circuit layouts that allow for improved cell size reduction without creating significant connection issues at high wiring levels thereby increasing circuit design flexibility.

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first M.sub.x layer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second M.sub.x layer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second M.sub.x layer interconnects are parallel. The MOS device further includes a first M.sub.x+1 layer interconnect extending in a second direction orthogonal to the first direction. The first M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The MOS device further includes a second M.sub.x+1 layer interconnect extending in the second direction. The second M.sub.x+1 layer interconnect is coupled to the first M.sub.x layer interconnect and the second M.sub.x layer interconnect. The second M.sub.x+1 layer interconnect is parallel to the first M.sub.x+1 layer interconnect.

A method for manufacturing a semiconductor structure includes defining active areas extending in an X-direction, arranged in a Y-direction, and on a substrate. Each of the active areas has nanostructures. The method further includes forming dummy gate structures across the active areas in the Y-direction, forming merged source/drain features in the active areas and on opposite sides of the dummy gate structures in the X-direction, forming dielectric structures in the active areas to cut each of the merged source/drain features into a first source/drain feature and a second source/drain feature, and to cut each of the dummy gate structures into segments, and replacing the segments of the dummy gate structures with gate structures wrapping around the nanostructures in the active areas. The dielectric structures are in contact with sidewalls of the first source/drain features, the second source/drain features, and the gate structures.

Techniques are disclosed for forming a compacted array of functional cells using next-generation lithography (NGL) processes, such as electron-beam direct write (EBDW) and extreme ultraviolet lithography (EUVL), to form the boundaries of the cells in the array. The compacted array of cells may be used for field-programmable gate array (FPGA) structures configured with logic cells, static random-access memory (SRAM) structures configured with bit cells, or other memory or logic devices having cell-based structures. The techniques can be used to gain a reduction in area of 10 to 50 percent, for example, for the array of functional cells, because the NGL processes allow for higher precision and closer cuts for the cell boundaries, as compared to conventional 193 nm photolithography. In addition, the use of NGL processes to form the boundaries for the cells may also reduce lithography induced variations that would otherwise be present with conventional 193 nm photolithography.