A semiconductor device (1) is manufactured which includes a SiC epitaxial layer (28), a plurality of transistor cells (18) that are formed in the SiC epitaxial layer (28) and that are subjected to ON/OFF control by a predetermined control voltage, a gate electrode (19) that faces a channel region (32) of the transistor cells (18) in which a channel is formed when the semiconductor device (1) is in an ON state, a gate metal (44) that is exposed at the topmost surface for electrical connection with the outside and that is electrically connected to the gate electrode (19) while being physically separated from the gate electrode (19), and a built-in resistor (21) that is made of polysilicon and that is disposed below the gate metal (44) so as to electrically connect the gate metal (44) and the gate electrode (19) together.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.

A semiconductor device including first and second active regions extending in a first direction; a field region between the first and second active regions; a gate structure including an upper gate electrode overlapping the first active region and extending in a second direction crossing the first direction, and a lower gate electrode overlapping the second active region, extending in the second direction, and on a same line as the upper gate electrode; a gate isolation layer between the upper and lower gate electrodes; source/drain regions on respective sides of the upper gate electrode; a contact jumper crossing the upper gate electrode in the first active region and electrically connecting the source/drain regions; and a first upper contact extending in the second direction in the field region and overlapping the lower gate electrode and the gate isolation layer, wherein the upper gate electrode is a dummy gate electrode.

An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region.

Semiconductor structures are provided. Each of the transistors includes a first source/drain region over a semiconductor fin extending in a first direction, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction perpendicular to the first direction. In a first transistor of the transistors, a first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors, A second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate extending in the second direction. A first contact of the first source/drain region is narrower than a second contact of the second source/drain region along the first direction.

Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

A semiconductor device includes a first gate electrode disposed on a substrate and extending in a first horizontal direction, a first gate contact and a dummy gate contact, which are spaced apart from each other in the first horizontal direction and are in contact with a top surface of the first gate electrode, a first interconnect line extending in a second horizontal direction and overlapping the first gate contact in a vertical direction with respect to the upper surface of the substrate, and a voltage generator configured to generate a first voltage and apply the first voltage to the first gate electrode via the first interconnect line and the first gate contact. The first gate electrode receives the first voltage via the first interconnect line and the first gate contact from the voltage generator. The dummy gate contact receives the first voltage via the first gate electrode.

Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.

A semiconductor device includes a standard cell, which includes first to fourth active areas that are extended in a first direction, first to fourth gate lines that are extended in a second direction perpendicular to the first direction over the first to fourth active areas and are disposed parallel to each other, a first cutting layer that is disposed between the first active area and the second active area and separates the second and third gate lines, a second cutting layer that is disposed between the third active area and the fourth active area and separates the second and third gate lines, a first gate contact that is formed on the second gate line separated by the first cutting layer and the second cutting layer, and a second gate contact that is formed on the third gate line separated by the first cutting layer and the second cutting layer.

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.