An integrated circuit (IC) device includes a circuit region, a lower metal layer over the circuit region, and an upper metal layer over the lower metal layer. The lower metal layer includes a plurality of lower conductive patterns elongated along a first axis. The upper metal layer includes a plurality of upper conductive patterns elongated along a second axis transverse to the first axis. The plurality of upper conductive patterns includes at least one input or output configured to electrically couple the circuit region to external circuitry outside the circuit region. The upper metal layer further includes a first lateral upper conductive pattern contiguous with and projecting, along the first axis, from a first upper conductive pattern among the plurality of upper conductive patterns. The first lateral upper conductive pattern is over and electrically coupled to a first lower conductive pattern among the plurality of lower conductive patterns.

A semiconductor device includes: a standard cell including a plurality of active patterns extending in a first direction, a gate structure intersecting the plurality of active patterns and extending in a second direction, and source/drain regions respectively provided on the plurality of active patterns positioned on both sides of the gate structure; a plurality of signal lines extending on the standard cell in the first direction, arranged in the second direction, and electrically connected to the standard cell; and first and second power straps extending on the standard cell in the first direction, electrically connected to some of the source/drain regions, and supplying power to the standard cell, wherein each of the first and second power straps is provided on the standard cell while provided on the same line as any one of the plurality of signal lines in the first direction.

A semiconductor structure is disclosed. The semiconductor structure includes: a first standard cell; and a second standard cell; wherein a cell width of the first standard cell along a first direction is substantially the same as a cell width of the second standard cell along the first direction, and a cell height of the first standard cell along a second direction perpendicular to the first direction is substantially greater than a cell height of the second standard cell along the second direction.

Various implementations described herein are directed to a device having a switch structure having an input and an output. The device may have a first thru-silicon via that couples a first backside signal to the input of the switch structure. The device may have a second thru-silicon via that couples a second backside signal to the output of the switch structure.

An integrated circuit includes first and second active regions extending in a first direction, a first gate line extending in a second direction substantially perpendicular to the first direction and crossing the first and second active regions, and a first contact jumper including a first conductive pattern intersecting the first gate line above the first active region and a second conductive pattern extending in the second direction above the first gate line and connected to the first conductive pattern.

Provided is an integrated circuit implemented by a plurality of vertical field effect transistors (VFETs) in one or more semiconductor cells, wherein a distance between a pair of second vertical channel structures of a first cell and an adjacent pair of first vertical channel structures in a second cell, all facing a cell boundary between the first and second cells, is the same as a distance between the pair of the first vertical channel structures and a pair of second vertical channel structures arranged next to the pair of the first vertical channel structures in the first cell.

An integrated circuit includes a plurality of metal lines extending along a first direction, the plurality of metal lines being separated, in a second direction perpendicular to the first direction, by integral multiples of a nominal minimum pitch. The integrated circuit further includes a plurality of standard cells, at least one of the plurality of standard cells having a cell height along the second direction being a non-integral multiple of the nominal minimum pitch.

A semiconductor standard cell of a flip-flop circuit includes semiconductor fins extending substantially parallel to each other along a first direction, electrically conductive wirings disposed on a first level and extending substantially parallel to each other along the first direction, and gate electrode layers extending substantially parallel to a second direction substantially perpendicular to the first direction and formed on a second level different from the first level. The flip-flop circuit includes transistors made of the semiconductor fins and the gate electrode layers, receives a data input signal, stores the data input signal, and outputs a data output signal indicative of the stored data in response to a clock signal, the clock signal is the only clock signal received by the semiconductor standard cell, and the data input signal, the clock signal, and the data output signal are transmitted among the transistors through at least the electrically conductive wirings.

A non-transitory computer-readable medium contains thereon a cell library. The cell library includes a plurality of cells configured to be placed in a layout diagram of an integrated circuit (IC). Each cell among the plurality of cells includes a first active region inside a boundary of the cell. The first active region extends along a first direction. At least one gate region is inside the boundary. The at least one gate region extends across the first active region along a second direction transverse to the first direction. A first conductive region overlaps the first active region and a first edge of the boundary. The first conductive region is configured to form an electrical connection to the first active region. The plurality of cells includes at least one cell a width of which in the first direction is equal to one gate region pitch between adjacent gate regions of the IC.

An IC includes a first set of MOS transistors configured to have a common first transistor source/drain terminal A, a first transistor gate, and a first transistor source/drain terminal B. In addition, the IC includes a first plurality of interconnect stacks coupled to the first transistor source/drain terminal A. Each interconnect stack of the first plurality of interconnect stacks extends in a second direction over at least a portion of the first set of MOS transistors and includes consecutive metal layer interconnects. Further, the IC includes a first comb interconnect structure extending in a first direction orthogonal to the second direction, with comb fingers extending in the second direction over at least a portion of the first set of MOS transistors and the first plurality of interconnect stacks. The first comb interconnect structure is coupled to the first plurality of interconnect stacks.