An arrayed switch circuitry includes contact units each of which includes a pad, a first row channel provided with a first switching element, a first column channel connected to the first row channel and provided with a second switching element, a connecting channel connecting the pad to the first row channel or the first column channel, a second row channel connected with the pad through a third switching element and a second column channel connected with the pad through a fourth switching element. The first row channels with the same row position are connected to each other, and the second row channels with the same row position are connected to each other. The first column channels with the same column position are connected to each other, and the second column channels with the same column position are connected to each other.

An integrated circuit cell is provided, which may include a substrate with a front side and a back side, an active region, a first via, and first, second and third conductive layers. A portion of the active region may be formed within the substrate. The first via and the first, second and third conductive layers are on the back side. The second and third conductive layers may be located further away from the substrate in a first direction than the first and second conductive layers, respectively. The depth of the first via may be greater than a distance between the second conductive layer and the third conductive layer. The integrated circuit cell may include a cell height in a second direction substantially perpendicular to the first direction. A width of the first via along the second direction may be between about 0.05 to about 0.25 times the cell height.

Technology is described for generating a valid token control signal from control signals from a row driver. In one example, a matrix type integrated circuit includes a row driver module and a 2D array of cell elements. The row driver module includes a voting logic module and at least two row drivers configured to generate control signals on at least two communal lines for cell elements of a row of the 2D array. Each row driver is configured to generate control signals on at least three control lines where at least two control lines are the communal lines and coupled to a corresponding communal line of another row driver. The voting logic module is coupled to the at least three control lines of one of the row drivers and configured to generate an output based on the control signals on the at least three control lines.

An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

A semiconductor device is provided. The semiconductor device includes a first-direction plurality of wirings extending in a first direction, and a second-direction plurality of wiring extending in a second direction intersecting the first direction. The first-direction plurality of wirings that extend in the first direction includes gate wirings spaced apart from each other in the second direction by a gate pitch, first wirings above the gate wirings spaced apart from each other in the second direction by a first pitch, second wirings above the first wirings spaced apart from each other in the second direction by a second pitch, and third wirings above the second wirings spaced apart from each other in the second direction by a third pitch. A ratio between the gate pitch and the second pitch is 6:5.

In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace.

A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

At least one method, apparatus and system disclosed involves circuit layout for comprising a unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.

A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.

A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell includes power post and ground posts in metal zero. The metal zero posts include no vias to any upper metal layers. Some variations of the standard cell have the power and ground posts routed in metal zero to a boundary edge of the standard cell. Layout rules are changed to allow this type of routing. The power and ground posts in metal zero are connected to power and ground posts in metal zero of a neighboring cell by abutment. The place-and-route tool doesn't need to perform a further routing step after placing the cells. For other variations, the power and ground posts are not routed to the boundary edge and the place-and-route tool routes power and ground connections in metal zero between the standard cell and the neighbor cell.