A method includes forming a cell layer including first and second cells, each of which is configured to perform a circuit function; forming a first metal layer above the cell layer and including a first conductive feature and a second conductive feature extending along a first direction, in which the first conductive feature extends from the first cell into the second cell, and in which a shortest distance between a center line of the first conductive feature and a center line of the second conductive feature along a second direction is less than a width of the first conductive feature, and the second direction is perpendicular to the first direction; forming a first conductive via interconnecting the cell layer and the conductive feature.

An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

A layout structure of a capacitive cell using forksheet FETs is provided. In transistors P3 and N3, VDD is supplied to a pair of pads and a gate interconnect, and VSS is supplied to a pair of pads and a gate interconnect. Capacitances are produced between nanosheets and the gate interconnect and between nanosheets and the gate interconnect. The faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect, and the faces of the nanosheets closer to the nanosheets are exposed from the gate interconnect.

A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

An integrated circuit chip including a substrate including first and second element regions; a first channel active region extending in a first direction; a second channel active region; gate lines extending in a second direction and intersecting the first and second channel active regions; a diffusion break extending in the second direction; source/drain regions at opposite sides of the gate lines and on the first and second channel active regions; a first power line electrically connected to the source/drain regions; and a second power line electrically connected to the source/drain regions and having a lower voltage level than the first power line, wherein the diffusion break includes a first region including an insulator and overlapping the first element region, and a second region including a same material as the gate lines and overlapping the second element region, wherein the second region is electrically connected to the second power line.

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device comprises a substrate, a conductive element disposed within a first region of the substrate, and a first transistor disposed within a second region adjacent to the first region of the substrate. The conductive element is electrically connected to an electrode of the first transistor, and the conductive element penetrates the substrate and is configured to receive a supply voltage.

A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

A semiconductor device includes first, second, and third power rails extending in a first direction on a substrate and sequentially spaced apart in a second direction intersecting the first direction. A fourth power rail extends in the first direction on the substrate between the first and third power rails. A first well of a first conductive type is displaced inside the substrate between the first and third power rails. Cells are continuously displaced between the first and third power rails and share the first well. The first and third power rails are provided with a first voltage, the second power rail is provided with a second voltage different from the first voltage, the fourth power rail is provided with a third voltage different from the first voltage and the second voltage, and the cells are provided with the third voltage from the fourth power rail.

A semiconductor device comprising a plurality of cells comprising cells of a first group, a second group and a third group is provided. The cell of the first group comprises a first power supply wiring for supplying a first potential, is located between the two cells of the third group and separated therefrom in a row direction by a distance, and supplies the first potential to the cells of the second group via a wiring on a front-side of the substrate. At least one of the two cells of the third group comprises a second power supply wiring for supplying a second potential having a polarity is opposite the first potential or being a ground. A third power supply wiring on a backside of a substrate supplies the first potential. The first power supply wiring comprises a via coupled to the third power supply wiring.

An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.