Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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29/00
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor;
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H01L29/66
Types of semiconductor device; ; Multistep manufacturing processes therefor
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H01L29/66007
Multistep manufacturing processes
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H01L29/66075
of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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H01L29/66227
the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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H01L29/66409
Unipolar field-effect transistors
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H01L29/66477
with an insulated gate, i.e. MISFET
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H01L29/66568
Lateral single gate silicon transistors
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H01L29/66575
where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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H01L29/66583
with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts
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H01L29/66583

FinFET and Method of Forming Same
20180040703 · 2018-02-08 ·

A FinFET device and a method of forming the same are provided. A method includes forming a patterned mask stack over a substrate, features of the patterned mask stack protecting the substrate having a uniform width. Unprotected portions of the substrate exposed by the patterned mask stack are removed to form a plurality of recesses in the substrate, unremoved portions of the substrate interposed between adjacent recesses forming a plurality of fins. Portions of the plurality of fins are removed, a width of a first fin of the plurality of fins being less than a width of a second fin of the plurality of fins.